Data processing system controlling bus access to an arbitrary sized memory area

Claim 2

A data processing system for accessing a memory via a bus, comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area within a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, and a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range; a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, a plurality of second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of said first string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit for controlling the bus access with the number of waits set by said second bit string in the case where the result of decision by said decision circuit indicates that said access address is included in the memory area of said predetermined range.

Claim 3

A data processing system according to claim 1, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 4

A data processing system according to claim 1, wherein said register stores a fifth bit where a value for invalidating predetermined bits in said register is set.

Claim 5

A data processing system to which are applied a first signal indicating the completion of each cycle of a bus access and a second signal indicating the number of waits of the bus access from a memory controller outside the system when accessing a memory via a bus, said system comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range in said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, and a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area; a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, a plurality of second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of the first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit for controlling the bus access to said memory area in the valid state of said fourth bit by the number of waits indicated by said second signal when said first signal is asserted before a time corresponding to the number of waits set by said second bit string passes, and by the number of waits set by said second bit string when said first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes.

Claim 6

A data processing system to which are applied a first signal indicating the completion of each cycle of a bus access and a second signal indicating the number of waits of the bus access from a memory controller outside the system when accessing a memory via a bus, said system comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range in said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, and a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area; a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, a plurality of second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of the first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit for controlling the bus access to said memory area in the valid state of said fourth bit by the number of waits indicated by said second signal when said first signal is asserted before a time corresponding to the number of waits set by said second bit string passes, and by the number of waits set by said second bit string when said first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes.

Claim 7

A data processing system according to claim 4, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 8

A data processing system according to claim 4, wherein said register stores a fifth bit where a value for invalidating predetermined bits in said register is set.

Claim 9

A data processing system for accessing a memory via a bus, comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range in said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, and a fourth bit for setting the validity/invalidity of the activation of a predetermined exception handling when accessing an inaccessible area; a decision circuit including a plurality of first gates each configured to perform an AND of respective bits of the predetermined number of bits of said access address and the third bit string, a plurality of Second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of said first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit for starting the predetermined exception handling after a time corresponding to the number of waits set by said second bit string passes when accessing an inaccessible area in the valid state of the fourth bit.

Claim 10

A data processing system for accessing a memory via a bus, comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range in said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, and a fourth bit for setting the validity/invalidity of the activation of a predetermined exception handling when accessing an inaccessible area; a decision circuit including a plurality of first gates each configured to perform an AND of respective bits of the predetermined number of bits of said access address and the third bit string, a plurality of Second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of said first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit for starting the predetermined exception handling after a time corresponding to the number of waits set by said second bit string passes when accessing an inaccessible area in the valid state of the fourth bit.

Claim 11

A data processing system according to claim 7, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 12

A data processing system according to claim 7, wherein said register stores a fifth bit where a value for invalidating predetermined bits in said register is set.

Claim 13

A data processing system to which are applied a first signal indicating the completion of each cycle of a bus access, a second signal for indicating the number of waits of the bus access and a third signal for starting a predetermined exception handling when accessing an inaccessible area, from a memory controller outside the system, said system comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area, and a fifth bit for setting the validity/invalidity of the activation of an exception handling when accessing an inaccessible area; a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, a plurality of second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of said first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit which operates when said memory area is accessed in the valid state of said fourth and fifth bits in such a manner that said exception handling is started by the number of waits indicated by said second bit string in the case where the first to third signals are asserted before a time corresponding to the number of waits set by said second bit string passes, said bus access is controlled by the number of waits set by said second bit string in the case where the first signal is asserted, but the second signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, said exception handling is started by the number of waits set by said second bit string in the case where the first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, whereas operating when an inaccessible area is accessed in the valid state of the fifth bit and in the invalid state of the fourth bit in such a manner that the exception handling is started after the time corresponding to the number of waits set by said second bit string passes.

Claim 14

A data processing system to which are applied a first signal indicating the completion of each cycle of a bus access, a second signal for indicating the number of waits of the bus access and a third signal for starting a predetermined exception handling when accessing an inaccessible area, from a memory controller outside the system, said system comprising: a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area, and a fifth bit for setting the validity/invalidity of the activation of an exception handling when accessing an inaccessible area; a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, a plurality of second gates each configured to decide coincidence between an output of a respective first gate and a corresponding bit of said first bit string and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; and a bus interface control circuit which operates when said memory area is accessed in the valid state of said fourth and fifth bits in such a manner that said exception handling is started by the number of waits indicated by said second bit string in the case where the first to third signals are asserted before a time corresponding to the number of waits set by said second bit string passes, said bus access is controlled by the number of waits set by said second bit string in the case where the first signal is asserted, but the second signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, said exception handling is started by the number of waits set by said second bit string in the case where the first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, whereas operating when an inaccessible area is accessed in the valid state of the fifth bit and in the invalid state of the fourth bit in such a manner that the exception handling is started after the time corresponding to the number of waits set by said second bit string passes.

Claim 15

A data processing system according to claim 10, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 16

A data processing system according to claim 10, wherein said register stores a sixth bit where a value for invalidating predetermined bits in said register is set.

Claim 17

A data processing system for accessing a memory via a bus, comprising: a plurality of memory area control circuits each capable of setting a plurality of memory areas to be controlled by bus access and each provided with a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area within a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, and a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range and a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; a circuit for determining the order of priority of a plurality of memory area control circuits and selecting a memory area control circuit of the highest priority in which an output of said third gate indicates the coincidence of all the outputs of said second gate with all the outputs of said first gate; a selection output circuit for outputting only data of said second bit string of the memory area control circuit selected by said selection circuit; and a bus interface control circuit for controlling the bus access on the basis of data of said second bit string output from said selection output circuit in the case where the memory area to be controlled by said selected memory area control circuit is accessed.

Claim 18

A data processing system for accessing a memory via a bus, comprising: a plurality of memory area control circuits each capable of setting a plurality of memory areas to be controlled by bus access and each provided with a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area within a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, and a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range and a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; a circuit for determining the order of priority of a plurality of memory area control circuits and selecting a memory area control circuit of the highest priority in which an output of said third gate indicates the coincidence of all the outputs of said second gate with all the outputs of said first gate; a selection output circuit for outputting only data of said second bit string of the memory area control circuit selected by said selection circuit; and a bus interface control circuit for controlling the bus access on the basis of data of said second bit string output from said selection output circuit in the case where the memory area to be controlled by said selected memory area control circuit is accessed.

Claim 19

A data processing system according to claim 13, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 20

A data processing system according to claim 13, wherein said register stores a fourth bit where a value for invalidating predetermined bits in said register is set.

Claim 21

A data processing system wherein a first signal indicating the completion of each cycle of a bus access, a second signal for indicating the number of waits of the bus access and a third signal for starting a predetermined exception handling when an inaccessible area is accessed are applied to a processor making access to a memory via a bus; said system comprising: a plurality of memory area control circuits each capable of setting a plurality of memory areas to be controlled by bus access and each provided with a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area, and a fifth bit for setting the validity/invalidity of the activation of an exception handling when accessing an inaccessible area and a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; a circuit for determining the order of priority of a plurality of memory area control circuits and selecting a memory area control circuit of the highest priority in which an output of the third gate indicates the coincidence of all the outputs of the second gate with all the outputs of said first gate; a selection output circuit for outputting only data of said second bit string and of said fifth bit of the memory area control circuit selected by said selection circuit; and a bus interface control circuit which operates, when the memory area set by said selected memory area control circuit is accessed in the valid state of the fourth and fifth bits in such a manner that said exception handling is started by the number of waits set by said second signal in the case where the first to third signals are asserted before a time corresponding to the number of waits set by said second bit string passes, the bus access is controlled by the number of waits set by said second bit string in the case where the first signal is asserted, but the second signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, said exception handling is started by the number of waits set by said second bit string in the case where the first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, whereas operating when an inaccessible area is accessed in the valid state of the fifth bit and in the invalid state of the fourth bit in such a manner that the exception handling is started after the time corresponding to the number of waits set by said second bit string passes.

Claim 22

A data processing system wherein a first signal indicating the completion of each cycle of a bus access, a second signal for indicating the number of waits of the bus access and a third signal for starting a predetermined exception handling when an inaccessible area is accessed are applied to a processor making access to a memory via a bus; said system comprising: a plurality of memory area control circuits each capable of setting a plurality of memory areas to be controlled by bus access and each provided with a register means for storing a first bit string of a predetermined number of most significant bits of a head address of a memory area in a predetermined range of said memory, a second bit string where the number of waits for access to said memory area is set, a third bit string for masking bits from the least significant bit of the predetermined number of the most significant bits of a to-be-accessed address correspondingly to a size of said memory area so as to specify a size of said predetermined range, a fourth bit for setting the validity/invalidity of the control of the bus access with reference to the first and second signals from said memory controller when accessing said memory area, and a fifth bit for setting the validity/invalidity of the activation of an exception handling when accessing an inaccessible area and a decision circuit including a plurality of first gates each configured to perform an AND operation of respective bits of the predetermined number of bits of said access address and said third bit string in order to mask the predetermined number of bits by said third bit string, and output a signal corresponding to said coincidence, and a third gate for deciding whether all the coincidence outputs from the plurality of second gates coincide with all the outputs of the plurality of first gates, said decision circuit deciding whether said access address is included in the memory area of said predetermined range; a circuit for determining the order of priority of a plurality of memory area control circuits and selecting a memory area control circuit of the highest priority in which an output of the third gate indicates the coincidence of all the outputs of the second gate with all the outputs of said first gate; a selection output circuit for outputting only data of said second bit string and of said fifth bit of the memory area control circuit selected by said selection circuit; and a bus interface control circuit which operates, when the memory area set by said selected memory area control circuit is accessed in the valid state of the fourth and fifth bits in such a manner that said exception handling is started by the number of waits set by said second signal in the case where the first to third signals are asserted before a time corresponding to the number of waits set by said second bit string passes, the bus access is controlled by the number of waits set by said second bit string in the case where the first signal is asserted, but the second signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, said exception handling is started by the number of waits set by said second bit string in the case where the first signal is not asserted before the time corresponding to the number of waits set by said second bit string passes, whereas operating when an inaccessible area is accessed in the valid state of the fifth bit and in the invalid state of the fourth bit in such a manner that the exception handling is started after the time corresponding to the number of waits set by said second bit string passes.

Claim 23

A data processing system according to claim 16, wherein said bus interface control circuit applies a signal showing that said memory area is the target for access to a circuit for decoding the access address in the case where an output of said third gate indicates that all the outputs of said second gate coincide with all the outputs of said first gate.

Claim 24

A data processing system according to claim 16, wherein said register stores a sixth bit where a value for invalidating predetermined bits in said register is set.