Integrated circuit device and microprocessor constituted thereby

Claim 2

An integrated circuit device which is constructed by sealing a semiconductor chip being able to be initialized in plural initial states in a package, wherein said package is constituted separately from said semiconductor chip and has a plurality of lead wires onto which a first potential and a second potential are applied, and said semiconductor chip has signal pads for electrically connecting itself and one of said plurality of lead wires of said package, and is initialized in any one of the plural initial states corresponding to connecting states of said signal pads and said plurality of lead wires when said semiconductor chip is sealed in said package.

Claim 3

The integrated circuit device of claim 1, wherein said package includes a first layer being coupled to lead wires onto which said first potential is applied, and a second layer being coupled to lead wires onto which said second potential is applied, said first and second layers being laminated in said package.

Claim 4

The integrated circuit device of claim 2, wherein said package includes a third layer onto which said plurality of lead wires is disposed to facilitate electrical connection with the signal pads of said semiconductor chip, said third layer being laminated in said package.

Claim 5

The integrated circuit device of claim 3, wherein said package includes additional lead wires for transmitting signals to and from said semiconductor chip, said additional lead wires being disposed on said third layer to facilitate electrical connection with the signal pads of said semiconductor chip.

Claim 6

The integrated circuit device of claim 4, wherein said semiconductor chip is initialized in any one of the plural initial states corresponding to connecting states of two signal pads and four lead wires.

Claim 7

The integrated circuit device of claim 5, wherein the plural initial states of said semiconductor chip correspond to various data bus widths of said chip.

Claim 8

The integrated circuit device which is constructed by sealing a semiconductor chip being able to be initialized in plural initial states in a package, wherein said package is constituted separately from said semiconductor chip, and wherein a first layer being coupled to lead wires onto which a first potential is applied, and a second layer being coupled to lead wires onto which a second potential is applied are laminated in said package, and said semiconductor chip has signal pads for electrically connecting itself and said lead wires coupled to said first layer and said second layer of said package, and is initialized in any one of the plural initial states corresponding to connecting states of said signal pads and said lead wires.

Claim 9

The integrated circuit device which is constructed by sealing a semiconductor chip being able to be initialized in plural initial states in a package, wherein said package is constituted separately from said semiconductor chip, and wherein a first layer being coupled to lead wires onto which a first potential is applied, and a second layer being coupled to lead wires onto which a second potential is applied are laminated in said package, and said semiconductor chip has signal pads for electrically connecting itself and said lead wires coupled to said first layer and said second layer of said package, and is initialized in any one of the plural initial states corresponding to connecting states of said signal pads and said lead wires.

Claim 10

The integrated circuit device of claim 7, wherein said package includes a third layer onto which said lead wires coupled to said first layer and said second layer of said package are disposed to facilitate electrical connection with the signal pads of said semiconductor chip, said third layer being laminated in said package.

Claim 11

The integrated circuit device of claim 8, wherein said package includes additional lead wires for transmitting signals to and from said semiconductor chip, said additional lead wires being disposed on said third layer to facilitate electrical connection with the signal pads of said semiconductor chip.

Claim 12

The integrated circuit device of claim 9, wherein said semiconductor chip is initialized in any one of the plural initial states corresponding to connecting states of two signal pads and four lead wires.

Claim 13

The integrated circuit device of claim 10, wherein the plural initial states of said semiconductor chip correspond to various data bus widths of said chip.

Claim 14

A microprocessor comprising an integrated circuit device which is constructed by sealing a semiconductor chip which is capable of being initialized in any one of a plurality of initial states in a package, wherein said package is constituted separately from said semiconductor chip and has a plurality of lead wires onto which a first potential and a second potential are applied; and said semiconductor chip is provided with signal pads for electrically connecting itself and said plurality of lead wires of said package, an instruction decoding circuit for decoding instructions, an instruction executing circuit for executing the instructions, and a control circuit which is initialized in any one of the plural initial states at resetting of said semiconductor chip corresponding to connecting states of said signal pads and said plurality of lead wires when said semiconductor chip is sealed in said package.

Claim 15

A microprocessor comprising an integrated circuit device which is constructed by sealing a semiconductor chip which is capable of being initialized in any one of a plurality of initial states in a package, wherein said package is constituted separately from said semiconductor chip and has a plurality of lead wires onto which a first potential and a second potential are applied; and said semiconductor chip is provided with signal pads for electrically connecting itself and said plurality of lead wires of said package, an instruction decoding circuit for decoding instructions, an instruction executing circuit for executing the instructions, and a control circuit which is initialized in any one of the plural initial states at resetting of said semiconductor chip corresponding to connecting states of said signal pads and said plurality of lead wires when said semiconductor chip is sealed in said package.

Claim 16

A microprocessor as set forth in claim 12, wherein a first layer being coupled to lead wires onto which said first potential is applied, and a second layer being coupled to lead wires onto which said second potential is applied are laminated in said package.

Claim 17

A microprocessor which executes one or more instructions and can be reset to an initial state, comprising an integrated circuit device which is constructed by sealing a semiconductor chip in a package; a data bus which inputs and outputs data to and from the exterior of said package; data bus width control value storing means for selecting an effective bit width of said data bus; signal pads into which signals for deciding the initial value of said data bus width control value storing means are inputted from the exterior; an instruction decoding circuit for decoding the instructions; a control circuit for setting the value inputted from said signal pads in said data bus width control value storing means at reset time; and an instruction executing circuit which inputs and outputs data to and from the exterior, through said data bus with the data bus width decided by the set value in said data bus width control value storing means, when the instructions decoded in said instruction decoding circuit are executed after resetting.

Claim 18

A microprocessor which executes one or more instructions and can be reset to an initial state, comprising an integrated circuit device which is constructed by sealing a semiconductor chip in a package; a data bus which inputs and outputs data to and from the exterior of said package; data bus width control value storing means for selecting an effective bit width of said data bus; signal pads into which signals for deciding the initial value of said data bus width control value storing means are inputted from the exterior; an instruction decoding circuit for decoding the instructions; a control circuit for setting the value inputted from said signal pads in said data bus width control value storing means at reset time; and an instruction executing circuit which inputs and outputs data to and from the exterior, through said data bus with the data bus width decided by the set value in said data bus width control value storing means, when the instructions decoded in said instruction decoding circuit are executed after resetting.

Claim 19

A microprocessor as set forth in claim 14, wherein a layer provided with signal lead wires connected to said data bus, and a layer provided with lead wires to which said signal pads are connected are laminated in said package.

Claim 20

A microprocessor which executes one or more instructions and can be reset to an initial state comprising an integrated circuit device which is constructed by sealing a semiconductor chip in a package; a data bus which inputs instructions from the exterior of said package; data bus width control value storing means for selecting an effective bit width of said data bus; an instruction fetch circuit which inputs the instructions from the exterior through said data bus; an instruction executing circuit for executing the instructions; and a control circuit for controlling execution of the instructions according to the output of said instruction decoding circuit; whereby when the data bus width change instruction is inputted through said data bus at the effective bit width decided by the set value in said data bus width control value storing means, the data bus width change instruction is decoded by said instruction decoding circuit and executed by said instruction executing circuit, to newly set the value in said data bus width control value storing means, and the instruction to be executed is inputted successively to said data bus width change instruction, through said data bus at the effective bit width decided by the set content.

Claim 21

A microprocessor which executes one or more instructions and can be reset to an initial state comprising an integrated circuit device which is constructed by sealing a semiconductor chip in a package; a data bus which inputs instructions from the exterior of said package; data bus width control value storing means for selecting an effective bit width of said data bus; an instruction fetch circuit which inputs the instructions from the exterior through said data bus; an instruction executing circuit for executing the instructions; and a control circuit for controlling execution of the instructions according to the output of said instruction decoding circuit; whereby when the data bus width change instruction is inputted through said data bus at the effective bit width decided by the set value in said data bus width control value storing means, the data bus width change instruction is decoded by said instruction decoding circuit and executed by said instruction executing circuit, to newly set the value in said data bus width control value storing means, and the instruction to be executed is inputted successively to said data bus width change instruction, through said data bus at the effective bit width decided by the set content.

Claim 22

A microprocessor as set forth in claim 16, wherein a plurality of layers including the layer being provided with the signal lead wires connected to said data bus are laminated in said package.

Claim 25

The apparatus of claim 18, further comprising two or more conductive pins protruding from the package; two or more pads on the chip; and a number of groups of conductive leads, wherein each pad has a unique associated group, each lead within a group being at a different voltage from other leads within the group, a lead within a given group associated with a given pad being positioned substantially near to the given pad such that a bonding wire may be directly connected from the given pad to each lead in the given group without contacting any other conductive surface; one or more common conductors within the package, leads at the same voltage being connected to the same common conductor, wherein each common conductor is electrically coupled to one of the pins; a bonding wire directly connected between each pad and one of the leads in the group associated with the pad, the bonding wires applying the voltage from the leads to the pads; detection means within the chip coupled to the pads for detecting the voltage applied by the bonding wires from the leads to the pads; and selection means within the chip coupled to the detection means for selectively setting one of a plurality of initial states within the chip in response to the detected voltages.

Claim 26

The apparatus of claim 19, wherein a lead may belong to two or more groups.