US4945472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor with I/O area detection
Assignee: Mitsubishi Electric Corp
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Filing: 1988-03-25
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Granted: 1990-07-31
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Expires: 2008-03-25
Abstract
Abstract A device for detecting whether addresses used for accessing in a memory mapped I/O system are present in the I/O area or not is provided. The device includes a mask register for logically ANDing with an incoming address. The output of the ANDing process is exclusive-ORed with an I/O address register. When an operand fetch is made to an I/O area the fetch is suspended during execution of preceding instructions. When the instruction fetch unit seeks an I/O area address, or the address calculation unit seeks an I/O area address, or data is fetched across a boundary of the I/O area, an exception is activated.
Inventors
- 👤 Ken Sakamura
- 👤 Souichi Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
115 words
A data processor whose I/O area is memory-mapped, comprising: a first register which stores an address for designating said I/O area; a second register which stores data for masking an address used for accessing; logical AND means coupled to said second register which obtains a masked address from said data stored in said second register and an address used for accessing; coincidence detection means coupled to said first register and said logical AND means which detects coincidence of said masked address obtained by said logical AND means and an address stored in said first register; and means, coupled to said detection means, for outputting a coincidence signal when said coincidence detection means detects said coincidence.
Claim 2
Dependent Claim
115 words
A data processor whose I/O area is memory-mapped, comprising: a first register which stores an address for designating said I/O area; a second register which stores data for masking an address used for accessing; logical AND means coupled to said second register which obtains a masked address from said data stored in said second register and an address used for accessing; coincidence detection means coupled to said first register and said logical AND means which detects coincidence of said masked address obtained by said logical AND means and an address stored in said first register; and means, coupled to said detection means, for outputting a coincidence signal when said coincidence detection means detects said coincidence.
Claim 3
Dependent Claim
44 words
A data processor whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said means for detecting, for prohibiting fetching instructions from said I/O area when said detecting means detects accessing to said I/O area.
Claim 4
Dependent Claim
44 words
A data processor whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said means for detecting, for prohibiting fetching instructions from said I/O area when said detecting means detects accessing to said I/O area.
Claim 5
Dependent Claim
78 words
A data processor whose I/O area is memory-mapped, the data processor having a device for accessing, including accessing to obtain data and accessing to obtain an instruction, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said means for detecting, for activating an exception when an instruction is executed and said detecting means detects accessing to said I/O area, and said accessing to said I/O area is an accessing to obtain an instruction.
Claim 6
Dependent Claim
78 words
A data processor whose I/O area is memory-mapped, the data processor having a device for accessing, including accessing to obtain data and accessing to obtain an instruction, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said means for detecting, for activating an exception when an instruction is executed and said detecting means detects accessing to said I/O area, and said accessing to said I/O area is an accessing to obtain an instruction.
Claim 7
Dependent Claim
95 words
A data processor of a data processing system, which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, and whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said detecting means, for prohibiting fetching data from said I/O area when said detecting means detects accessing to said I/O area, and when said data is an address of an operand.
Claim 8
Dependent Claim
95 words
A data processor of a data processing system, which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, and whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; and means, coupled to said detecting means, for prohibiting fetching data from said I/O area when said detecting means detects accessing to said I/O area, and when said data is an address of an operand.
Claim 9
Dependent Claim
111 words
A data processor of a data processing system, which is provided with an instruction for accessing an operand under an indirect memory addressing mode, and having an addressable memory for storing information, and a memory-mapped I/O area, comprising: means for accessing said I/O area; and means, coupled to said means for accessing, for accessing a first address for an indirect memory addressing mode in which information stored in said addressable memory at said first address indicates a second address which contains data, and for starting an exception when an instruction is executed whose operand is the data existing at said second address, and said first address is in said I/O area.
Claim 10
Dependent Claim
111 words
A data processor of a data processing system, which is provided with an instruction for accessing an operand under an indirect memory addressing mode, and having an addressable memory for storing information, and a memory-mapped I/O area, comprising: means for accessing said I/O area; and means, coupled to said means for accessing, for accessing a first address for an indirect memory addressing mode in which information stored in said addressable memory at said first address indicates a second address which contains data, and for starting an exception when an instruction is executed whose operand is the data existing at said second address, and said first address is in said I/O area.
Claim 11
Dependent Claim
78 words
A data processor having a memory-mapped I/O area, comprising: means for detecting accessing to said I/O area; means, coupled to said means for detecting, for activating an exception when data comprised of a plurality of bytes is accessed, said data being a single data, and at least a first of said plurality of bytes exists in said I/O area and at least a second of said plurality of bytes exists in an area other than said I/O area.
Claim 12
Dependent Claim
78 words
A data processor having a memory-mapped I/O area, comprising: means for detecting accessing to said I/O area; means, coupled to said means for detecting, for activating an exception when data comprised of a plurality of bytes is accessed, said data being a single data, and at least a first of said plurality of bytes exists in said I/O area and at least a second of said plurality of bytes exists in an area other than said I/O area.
Claim 13
Dependent Claim
100 words
A data processor of a data processing system whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; an execution unit which executes instructions; an operand fetch unit, coupled to said execution unit, which performs fetching of operands of said instructions, wherein said fetching of operands of at least one instruction causes accessing of said I/O area; and means, coupled to said operand fetch unit, and said detecting means for suspending said operand fetch unit from accessing said I/O area caused by a second instruction until said execution unit completes execution of a preceding instruction.
Claim 14
Dependent Claim
100 words
A data processor of a data processing system whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; an execution unit which executes instructions; an operand fetch unit, coupled to said execution unit, which performs fetching of operands of said instructions, wherein said fetching of operands of at least one instruction causes accessing of said I/O area; and means, coupled to said operand fetch unit, and said detecting means for suspending said operand fetch unit from accessing said I/O area caused by a second instruction until said execution unit completes execution of a preceding instruction.
Claim 15
Dependent Claim
135 words
A data processor of a data processing system which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; means, coupled to said detecting means for prohibiting fetching data from said I/O area when said detecting means detects accessing to said I/O area and when said data is an address of an operand; and means, coupled to said detecting means for activating an exception when an instruction is executed and said detecting means detects accessing to said I/O area, and said instruction is an instruction for accessing an operand under an indirect memory addressing mode.
Claim 16
Dependent Claim
135 words
A data processor of a data processing system which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, whose I/O area is memory-mapped, comprising: detecting means for detecting accessing to said I/O area; means, coupled to said detecting means for prohibiting fetching data from said I/O area when said detecting means detects accessing to said I/O area and when said data is an address of an operand; and means, coupled to said detecting means for activating an exception when an instruction is executed and said detecting means detects accessing to said I/O area, and said instruction is an instruction for accessing an operand under an indirect memory addressing mode.
Claim 17
Independent Claim
38 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; and prohibiting fetching an instruction from said I/O area when accessing to said I/O area is detected.
Claim 18
Independent Claim
38 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; and prohibiting fetching an instruction from said I/O area when accessing to said I/O area is detected.
Claim 19
Independent Claim
73 words
A method for accessing data in a data processor whose I/O area is memory-mapped, the data processor having a device for accessing, including accessing to obtain data and accessing to obtain an instruction, the method comprising: detecting accessing to said I/O area; and activating an exception when an instruction is executed and accessing to said I/O area is detected, and said accessing to said I/O area is an addressing to obtain an instruction.
Claim 20
Independent Claim
73 words
A method for accessing data in a data processor whose I/O area is memory-mapped, the data processor having a device for accessing, including accessing to obtain data and accessing to obtain an instruction, the method comprising: detecting accessing to said I/O area; and activating an exception when an instruction is executed and accessing to said I/O area is detected, and said accessing to said I/O area is an addressing to obtain an instruction.
Claim 21
Independent Claim
83 words
A method for accessing data in a data processor which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; and prohibiting fetching data from said I/O area when accessing to said I/O area is detected, and when said data is an address of an operand.
Claim 22
Independent Claim
83 words
A method for accessing data in a data processor which is provided with an instruction for accessing an operand under an indirect memory addressing mode, the data processor having a device for fetching data, including fetching an operand and fetching an address of an operand, whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; and prohibiting fetching data from said I/O area when accessing to said I/O area is detected, and when said data is an address of an operand.
Claim 23
Independent Claim
69 words
A method for accessing data in a data processor which is provided with an instruction for accessing an operand under an indirect memory addressing mode, whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; prohibiting fetching data from said I/O area when accessing to said I/O area is detected; and activating an exception when an instruction is executed and accessing to said I/O area is detected.
Claim 24
Independent Claim
69 words
A method for accessing data in a data processor which is provided with an instruction for accessing an operand under an indirect memory addressing mode, whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; prohibiting fetching data from said I/O area when accessing to said I/O area is detected; and activating an exception when an instruction is executed and accessing to said I/O area is detected.
Claim 25
Independent Claim
73 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: activating an exception when a plurality of bytes is accessed, said plurality of bytes being one of a single operand and a single address, and at least a first of said plurality of bytes exists in said I/O area and at least a second of said plurality of bytes exists in an area other than said I/O area.
Claim 26
Independent Claim
73 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: activating an exception when a plurality of bytes is accessed, said plurality of bytes being one of a single operand and a single address, and at least a first of said plurality of bytes exists in said I/O area and at least a second of said plurality of bytes exists in an area other than said I/O area.
Claim 27
Independent Claim
78 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; providing an execution unit which executes instructions; providing an operand fetch unit which fetches operands of instructions wherein said fetching of operands for an instruction causes accessing of said I/O area; and suspending said operand fetch unit from accessing said I/O area caused by an instruction until said execution unit completes the execution of a preceding instruction.
Claim 28
Independent Claim
78 words
A method for accessing data in a data processor whose I/O area is memory-mapped, comprising: detecting accessing to said I/O area; providing an execution unit which executes instructions; providing an operand fetch unit which fetches operands of instructions wherein said fetching of operands for an instruction causes accessing of said I/O area; and suspending said operand fetch unit from accessing said I/O area caused by an instruction until said execution unit completes the execution of a preceding instruction.
Claim 29
Independent Claim
135 words
A method for accessing data in a data processing system having an addressable memory for storing information, and a memory-mapped I/O system, comprising: providing a data processor having means for fetching information stored in said addressable memory at one of a plurality of memory addresses defining an address space, wherein a portion of said address space is an I/O area of the memory-mapped I/O system, and wherein at least one of said plurality of memory addresses is within said I/O area of said address space; providing a detection unit connected to said data processor; sending to said detection unit an indication of a first address to be fetched; determining whether said first address is in said I/O area, using said detection unit; and providing a first signal when said address is in said I/O area.
Claim 30
Independent Claim
135 words
A method for accessing data in a data processing system having an addressable memory for storing information, and a memory-mapped I/O system, comprising: providing a data processor having means for fetching information stored in said addressable memory at one of a plurality of memory addresses defining an address space, wherein a portion of said address space is an I/O area of the memory-mapped I/O system, and wherein at least one of said plurality of memory addresses is within said I/O area of said address space; providing a detection unit connected to said data processor; sending to said detection unit an indication of a first address to be fetched; determining whether said first address is in said I/O area, using said detection unit; and providing a first signal when said address is in said I/O area.
Claim 31
Dependent Claim
88 words
A method, as claimed in claim 15, further comprising: indirectly addressing a memory location by fetching the contents of a first of said plurality of memory addresses and subsequently fetching the contents of a second of said plurality of memory addresses whose address is indicated by the contents of said first of said plurality of memory addresses; and voiding said fetching of the contents of said first memory address when said first signal indicates that said first of said plurality of memory addresses is within said I/O area.
Claim 32
Dependent Claim
60 words
A method, as claimed in claim 15, wherein said step of providing a data processor includes providing an execution unit for executing instructions and instruction fetch means for fetching an instruction for execution by said execution unit from a specified memory address and further comprising: voiding said fetching of an instruction when said specified address is within said I/O area.
Claim 33
Dependent Claim
79 words
A method, as claimed in claim 15, wherein said step of providing a data processor comprises providing means for fetching a single operand or a single operand address, comprising a plurality of bytes, the method further comprising: activating an exception when said first signal indicates that at least a first of said plurality of bytes exists in said I/O area and at least a second of said plurality of bytes is in an area other than said I/O area.
Claim 34
Dependent Claim
109 words
A method, as claimed in claim 15, wherein said step of providing a data processor comprises providing an operand fetch unit for accessing a memory location to prefetch an operand and an execution unit for executing one of a plurality of instructions; and further comprising: suspending operation of said operand fetch unit for said prefetching an operand of a second instruction, said operand of said second instruction having an operand address, until the execution of a first instruction in said execution unit is completed, if said operand address is in said I/O area while said execution unit is executing a first instruction which was previous to said second instruction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |