Instruction prefetch system

Claim 1

A pipelining information processor comprising: (a) a memory; (b) an instruction buffer coupled to said memory so as to receive prefetched instructions from said memory; (c) means for executing instructions; (d) a memory access unit including: (i) an address generator coupled to receive an input from said instruction buffer and to generate therefrom a logical address output; and (ii) means for address modification receiving a logical address as an input and providing a physical address output to said memory; (e) means for fetching an instruction from said instruction buffer to said means for executing; (f) means, operating in parallel with said means for fetching, for providing an input to said means for address modification including: (i) first means to detect if the input provided to said address generator requires a memory access to obtain an operand, and to cause said means for providing to couple the output of said address generator to said means for address modification if the input requires a memory access; and (ii) second means to detect a need to prefetch an instruction to said instruction buffer, and to cause said means for providing to couple an address of an instruction to be prefetched to said means for address modification, if said second means to detect detects said need and if said first means to detect does not detect that the input provided to said address generator requires a memory access to obtain an operand, whereby fetching of an instruction for execution and prefetching an instruction to said instruction buffer occurs simultaneously; and (g) control means for sequentially moving instruction addresses through said means for providing, said instruction buffer, said address generator, and said means for address modification in response to a series of clock pulses in such a manner that address generation, address modification, instruction fetching, and instruction execution occurs in parallel on successive instruction.