System for reallocation of memory banks in memory sized order

Claim 2

A computer system comprising: a plurality of memory banks to which a plurality of access control signals are respectively assigned and which are independently accessible; an address decoder for detecting coincidence or non-coincidence of a plurality of decoding conditions, corresponding to said plurality of access control signals and set in said address decoder, with a memory address from a CPU, and enabling an access control signal line corresponding to a coincident decoding condition to thereby select a memory bank; means for detecting memory sizes of said plurality of memory banks; memory reallocation means for reallocating said plurality of memory banks in a memory address space of said CPU in a memory-size order in such a way that a memory bank with a larger memory size is allocated in smaller addresses in the memory address space and determining memory address ranges to be respectively allocated to said plurality of memory banks in accordance with the reallocated memory arrangement; and means for detecting a sequence of bits commonly present only in binary data indicating all memory address values belonging to a memory address range corresponding to each of said memory banks, and setting said sequence of bits in said address decoder as a decoding condition of each of said access control signal lines.

Claim 3

The computer system according to claim 1, wherein said address decoder includes: registers in which plural sequences of bits indicating a plurality of decoding conditions respectively corresponding to said plurality of access control signal lines are set; and a plurality of decoding circuits provided in association with said plurality of access control signal lines, each decoding circuit detecting coincidence or non-coincidence of a sequence of bits indicating a decoding condition of an associated access control signal line with a memory address from said CPU and enabling said access control signal line when there is a coincidence.

Claim 4

The computer system according to claim 1, further comprising: means for determining a combination of two or more memory banks interleavable page by page in accordance with a memory arrangement of said plurality of memory banks; and means for changing decoding conditions of access control signal lines corresponding to memory banks belonging to said combination in such a way that those memory banks are alternately accessed page by page, in accordance with a sequence of bits commonly present in an entire address range for said memory banks and a predetermined sequence of bits between an address of each memory bank in a page and a page designating address.

Claim 5

The computer system according to claim 1, wherein each of said memory banks is a DRAM bank constituted of a plurality of DRAM chips; and each of said access control signal lines is a row address strobe signal line commonly connected to said DRAM chips of said DRAM bank.

Claim 6

The computer system according to claim 4, wherein said memory size detecting means includes means for detecting at least one of a column address size and a row address size of each DRAM bank and determining a memory size of each DRAM bank based on said detected address size.

Claim 7

The computer system according to claim 4, further comprising address output means for separating a memory address from said CPU into a row address and a column address corresponding to a DRAM bank to be accessed, said address output means including: registers in which a plurality of parameter values for designating an extraction start position for extracting said row address from said memory address for each of said access control signal line; and means for selecting one parameter value from said registers in accordance with a row address strobe signal line enabled by said address decoder and extracting said row address from said memory address in accordance with said selected parameter value.

Claim 8

The computer system according to claim 4, further comprising address output means for separating a memory address from said CPU into a row address and a column address corresponding to a DRAM bank to be accessed, said address output means including: registers in which a plurality of parameter values for designating an extraction start position for extracting said row address from said memory address for each of said access control signal line; a plurality of row address extraction means for respectively extracting row addresses from said memory address in accordance with said plurality of parameter values set in said registers; and means, connected at a subsequent stage of said plurality of row address extraction means, for selecting one of outputs of said plurality of row address extraction means in accordance with a row address strobe signal line enabled by said address decoder.

Claim 9

The computer system according to claim 4, wherein a reserve area is secured in said memory address spaces for allocation of other memories than said plurality of DRAM banks; address conversion means, further provided at a preceding stage of said address decoder, for converting a memory address from said CPU to a DRAM logical address exclusive for DRAM banks in accordance with a memory map of said CPU in such a manner that memory addresses allocated to DRAM banks allocated immediately preceding and following said reserve area are consecutive between those DRAM banks; and said address decoder detects coincidence or non-coincidence of said DRAM logical address converted by said address conversion means with each of said decoding conditions.

Claim 10

The computer system according to claim 4, further comprising page hit determining means for holding a memory address from said CPU at a time of a previous memory access, compares said held memory address with a memory address from said CPU at a time of a next memory access, and determines presence or absence of a page hit in accordance with a result of that comparison.

Claim 11

A computer system comprising: an internal memory installed on a system board and constituted of one or more DRAM banks respectively connected to a plurality of first row address strobe signal lines; an expansion memory detachably installed to an expansion memory connector and constituted of one or more DRAM banks respectively connected to a plurality of second row address strobe signal lines different from those of said internal memory; an address decoder for detecting coincidence or non-coincidence of a plurality of decoding conditions, corresponding to said plurality of first and second row address strobe signal lines and set in said address decoder, with a memory address from a CPU, and enabling a row address strobe signal line corresponding to a coincident decoding condition to thereby select one DRAM bank included in said internal memory and expansion memory; and initializing means for initializing said address decoder in response to activation of said computer system, said initializing means including, means for detecting memory sizes of said DRAM banks included in said internal memory and expansion memory, memory reallocation means for reallocating said plurality of DRAM banks in memory address spaces of said CPU in a memory-size order in such a way that a DRAM bank with a larger memory size is allocated in a smaller memory address space and determining memory address ranges to be respectively allocated to said plurality of DRAM banks in accordance with the reallocated memory arrangement, and means for detecting a sequence of bits commonly present only in binary data indicating all memory address values belonging to a memory address range corresponding to each of said DRAM banks, and setting said sequence of bits in said address decoder as a decoding condition of each of said row address strobe signal lines.

Claim 12

A computer system comprising: an internal memory installed on a system board and constituted of one or more DRAM banks respectively connected to a plurality of first row address strobe signal lines; an expansion memory detachably installed to an expansion memory connector and constituted of one or more DRAM banks respectively connected to a plurality of second row address strobe signal lines different from those of said internal memory; an address decoder for detecting coincidence or non-coincidence of a plurality of decoding conditions, corresponding to said plurality of first and second row address strobe signal lines and set in said address decoder, with a memory address from a CPU, and enabling a row address strobe signal line corresponding to a coincident decoding condition to thereby select one DRAM bank included in said internal memory and expansion memory; and initializing means for initializing said address decoder in response to activation of said computer system, said initializing means including, means for detecting memory sizes of said DRAM banks included in said internal memory and expansion memory, memory reallocation means for reallocating said plurality of DRAM banks in memory address spaces of said CPU in a memory-size order in such a way that a DRAM bank with a larger memory size is allocated in a smaller memory address space and determining memory address ranges to be respectively allocated to said plurality of DRAM banks in accordance with the reallocated memory arrangement, and means for detecting a sequence of bits commonly present only in binary data indicating all memory address values belonging to a memory address range corresponding to each of said DRAM banks, and setting said sequence of bits in said address decoder as a decoding condition of each of said row address strobe signal lines.

Claim 13

A computer system comprising: a CPU; plural types of memory devices; a plurality of memory controllers, respectively coupled to said plural types of memory devices, for controlling access to said memory devices; a register file including a plurality of I/O control registers provided in association with a plurality of memory address areas constituting memory address space addressable by said CPU, each register being set with attribute information designating a type of a memory device to be allocated in an associated memory address area, wherein said attribute information is either read attribute information designating a type of a memory device whose read access is to be permitted or write attribute information designating a type of a memory device whose write access is to be permitted; and decoding means, coupled to said register file, for determining a memory device targeted for a read access or a write access in accordance with the read or write attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a read access or a write access to execute a memory access, when said CPU executes a memory read cycle or a memory write cycle.

Claim 14

A computer system comprising: a CPU; plural types of memory devices; a plurality of memory controllers, respectively coupled to said plural types of memory devices, for controlling access to said memory devices; a register file including a plurality of I/O control registers provided in association with a plurality of memory address areas constituting memory address space addressable by said CPU, each register being set with attribute information designating a type of a memory device to be allocated in an associated memory address area, wherein said attribute information is either read attribute information designating a type of a memory device whose read access is to be permitted or write attribute information designating a type of a memory device whose write access is to be permitted; and decoding means, coupled to said register file, for determining a memory device targeted for a read access or a write access in accordance with the read or write attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a read access or a write access to execute a memory access, when said CPU executes a memory read cycle or a memory write cycle.

Claim 15

The computer system according to claim 11, wherein said plural types of memory devices include a RAM device connected to a first bus, and a ROM device connected to a second bus narrower than said first bus.

Claim 16

The computer system according to claim 12, wherein said plurality of memory controllers includes a first memory controller for controlling access to said RAM device and a second memory controller for controlling access to said ROM device.

Claim 17

The computer system according to claim 12, wherein said RAM device is a 32-bit device and said ROM device is an 8-bit or 16-bit device.

Claim 18

A computer system comprising: a CPU; a RAM device and a ROM device; first and second memory controllers, respectively coupled to said RAM device and ROM device, for controlling access to said RAM device and ROM device; a register file including a plurality of I/O control registers provided in association with a plurality of memory address areas constituting memory address space addressable by said CPU, each register being set with attribute information including read attribute information designating a type of a memory device among said RAM device and ROM device which is to be allocated in a memory address area associated with that register and whose read access is to be permitted and write attribute information designating a type of a memory device among said RAM device and ROM device which is to be allocated in a memory address area associated with that register and whose write access is to be permitted; and decoding means, coupled to said register file, for instructing one of said first and second memory controllers in accordance with said attribute information of a memory address area corresponding to a value of a memory address from said CPU when said CPU executes a bus cycle for a memory access, said decoding means including, means for determining a memory device targeted for a read access in accordance with said read attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a read access to execute a memory access, when said bus cycle is a memory read cycle, and means for determining a memory device targeted for a write access in accordance with said write attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a write access to execute a memory access, when said bus cycle is a memory write cycle.

Claim 19

A computer system comprising: a CPU; a RAM device and a ROM device; first and second memory controllers, respectively coupled to said RAM device and ROM device, for controlling access to said RAM device and ROM device; a register file including a plurality of I/O control registers provided in association with a plurality of memory address areas constituting memory address space addressable by said CPU, each register being set with attribute information including read attribute information designating a type of a memory device among said RAM device and ROM device which is to be allocated in a memory address area associated with that register and whose read access is to be permitted and write attribute information designating a type of a memory device among said RAM device and ROM device which is to be allocated in a memory address area associated with that register and whose write access is to be permitted; and decoding means, coupled to said register file, for instructing one of said first and second memory controllers in accordance with said attribute information of a memory address area corresponding to a value of a memory address from said CPU when said CPU executes a bus cycle for a memory access, said decoding means including, means for determining a memory device targeted for a read access in accordance with said read attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a read access to execute a memory access, when said bus cycle is a memory read cycle, and means for determining a memory device targeted for a write access in accordance with said write attribute information of a memory address area corresponding to a value of a memory address from said CPU and instructing one of said memory controllers which is associated with said memory device targeted for a write access to execute a memory access, when said bus cycle is a memory write cycle.

Claim 20

The computer system according to claim 15, further comprising: means for, in response to activation of said computer system, setting attribute information including read attribute information designating said ROM device and write attribute information designating said RAM device in one of said I/O control register of said register file which is associated with memory address space where said ROM device is to be allocated, thereby allocating said ROM device and RAM device in same memory address space; means for sequentially reading from a head address to an end address in said memory address space where said ROM device and RAM device are allocated, and sequentially writing read data at same addresses, thereby copying contents of said ROM device into said RAM device; and attribute information changing means for changing read attribute information designating said ROM device to a value designating said RAM device to nullify access to said ROM device.

Claim 21

The computer system according to claim 15, wherein said attribute information includes write protect information designating whether or not to inhibit writing to said RAM device when said write attribute information designates said RAM device as a memory device whose write access is to be permitted; and said decoding means further includes means for causing said first memory controller to inhibit a write access to said RAM device when said attribute information includes write protect information designating inhibition of writing to said RAM device.

Claim 22

The computer system according to claim 17, further comprising: means for, in response to activation of said computer system, setting attribute information including read attribute information designating said ROM device and write attribute information designating said RAM device in one of said I/O control register of said register file which is associated with memory address space where said ROM device is to be allocated, thereby allocating said ROM device and RAM device in same memory address space; means for sequentially reading from a head address to an end address in said memory address space where said ROM device and RAM device are allocated, and sequentially writing read data at same addresses, thereby copying contents of said ROM device into said RAM device; attribute information changing means for changing read attribute information designating said ROM device to a value designating said RAM device to nullify access to said ROM device; and means for setting write protect information designating inhibition of writing to said RAM device in said I/O control registers in order to change access permission to said RAM device only to a read access.

Claim 23

The computer system according to claim 17, wherein said ROM device is a system ROM having stored a BIOS routine for controlling hardware of said computer system.

Claim 24

The computer system according to claim 15, wherein said RAM device is connected to a first bus, and said ROM device is connected to a second bus narrower than said first bus.

Claim 25

The computer system according to claim 17, wherein said first memory controller controls access to said RAM device at a timing corresponding to a bus cycle of said first bus and said second memory controller controls access to said ROM device at a timing corresponding to a bus cycle of said second bus.