Method of fabricating MOSFET devices

Claim 1

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; and completing the fabrication of said integrated circuit device, including the step of depositing an insulating layer overlying said gate electrodes and said titanium silicide.

Claim 2

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; and completing the fabrication of said integrated circuit device, including the step of depositing an insulating layer overlying said gate electrodes and said titanium silicide.

Claim 10

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; annealing said substrate to transform said titanium silicide from C49 phase to C54 phase titanium silicide; depositing an insulating layer overlying said gate electrodes and said titanium silicide; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device.

Claim 11

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; annealing said substrate to transform said titanium silicide from C49 phase to C54 phase titanium silicide; depositing an insulating layer overlying said gate electrodes and said titanium silicide; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device.

Claim 19

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing polysilicon gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; growing first thermal oxide insulating spacers on the sidewalls of said gate electrodes; depositing a layer of silicon nitride over the surface of said substrate and anisotropically etching to leave said silicon nitride layer as second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby C49-TiSi 2 is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers; removing said elemental titanium; annealing said substrate to transform said C49-TiSi 2 into C54-TiSi 2 wherein said C54-TiSi 2 overlying said source and drain regions reduces said source and drain resistance; depositing an insulating layer overlying said gate electrodes and said C54-TiSi 2 ; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device.

Claim 20

A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing polysilicon gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; growing first thermal oxide insulating spacers on the sidewalls of said gate electrodes; depositing a layer of silicon nitride over the surface of said substrate and anisotropically etching to leave said silicon nitride layer as second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby C49-TiSi 2 is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers; removing said elemental titanium; annealing said substrate to transform said C49-TiSi 2 into C54-TiSi 2 wherein said C54-TiSi 2 overlying said source and drain regions reduces said source and drain resistance; depositing an insulating layer overlying said gate electrodes and said C54-TiSi 2 ; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device.