Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same

Claim 2

A memory subsystem comprising: processing circuitry; first and second banks of memory, each said bank including a predetermined number of primary memory cells and a predetermined number of redundant memory cells; a primary address bus for allowing said processing circuitry to address at least one of said primary memory cells, said at least one primary memory cell residing in a primary cell memory space; and a redundancy bus for allowing said processing circuitry to address at least one of said redundancy cells, said at least one redundancy cell residing in a redundacy cell memory space separate from said primary cell memory space.

Claim 3

The memory subsystem of claim 1 wherein each of said banks includes an array of rows and columns of primary memory cells, at least one column of redundant memory cells, and at least one row of redundant memory cells.

Claim 4

The memory subsystem of claim 2 wherein each said array is associated with address decoder circuitry for addressing said rows and columns of memory cells, said address decoder circuitry comprising: primary row decoder logic for selecting for access a said one of said primary rows in response to address bits presented on said primary address bus; primary column decoder logic for selecting for access a said one of said primary columns in response to address bits presented on said primary address bus; redundancy row decoder logic for selecting for access a said one of said redundant rows in response to address bits presented on said redundancy bus; and redundancy column decoder logic for selecting for access a said one of said redundant columns in response to address bits presented on said redundancy bus.

Claim 5

The memory subsystem of claim 1 wherein said primary address bus comprises a non-multiplexed bus.

Claim 6

The memory subsystem of claim 1 wherein said redundancy bus comprises a non-multiplexed bus.

Claim 7

The memory subsystem of claim 1 wherein said memory cells comprise dynamic random access memory cells.

Claim 8

The memory subsystem of claim 1 wherein said processing circuitry and said first and second memory banks are fabricated on a single integrated circuit chip.

Claim 9

The memory subsystem of claim 1 wherein said processing circuitry comprises a display controller.

Claim 10

A memory device comprising: information processing circuitry; a plurality of arrays of rows and columns of memory cells, each said array including a preselected number of primary rows and columns and a preselected number of redundant rows and columns; first address logic for individually addressing said primary rows and columns of cells in response to bits presented by said processing circuitry on a primary address bus, said bits presented on said primary address bus defining a primary address space in which said primary rows and columns reside; second address logic for individually addressing said redundant rows and columns in response to bits presented by said processing circuitry on a redundancy bus, said bits presented on said redundancy bus defining a redundancy address space in which said redundant rows and columns reside.

Claim 11

A memory device comprising: information processing circuitry; a plurality of arrays of rows and columns of memory cells, each said array including a preselected number of primary rows and columns and a preselected number of redundant rows and columns; first address logic for individually addressing said primary rows and columns of cells in response to bits presented by said processing circuitry on a primary address bus, said bits presented on said primary address bus defining a primary address space in which said primary rows and columns reside; second address logic for individually addressing said redundant rows and columns in response to bits presented by said processing circuitry on a redundancy bus, said bits presented on said redundancy bus defining a redundancy address space in which said redundant rows and columns reside.

Claim 12

The memory device of claim 9 wherein said bits presented on said primary address bus comprise at least one location address bit and at least one bank select bit.

Claim 13

The memory device of claim 10 wherein said at least one location address bit comprises a plurality of row and column address bits presented on said primary address bus in a non-multiplexed format.

Claim 14

The memory device of claim 9 wherein said bits presented on said redundancy address comprise at least one location address bit, at least one bank select bit, and at least one redundancy address bit.

Claim 15

The memory device of claim 12 wherein said at least one location address bit comprises a plurality of row and column address bits presented on said redundancy bus in a non-multiplexed format.

Claim 16

The memory device of claim 9 wherein said first address logic comprises a plurality of row decoders and a plurality of column decoders coupled to said primary address bus, each of said row and column decoders including disabling circuitry.

Claim 17

The memory device of claim 14 wherein each of said row and column decoders effectuate NOR logic in response to said bits received on said primary address bus.

Claim 18

The memory device of claim 14 wherein said disabling circuitry comprises a programable link.

Claim 19

The memory device of claim 9 wherein said second address logic comprises a plurality of redundant row decoders and a plurality of redundant column decoders coupled to said redundancy bus, each of said decoders including programing circuitry for controlling a response to said bits presented on said redundancy bus.

Claim 20

The memory device of claim 17 wherein each of said redundant row and redundant column decoders effectuate a NOR logic in response to said bits received on said redundancy address bus.

Claim 21

The memory device of claim 17 wherein said programming circuitry comprises a plurality of programmable links.

Claim 22

A processing system comprising: a controller; a redundancy bus; a memory comprising: a plurality of memory banks each comprising an array of memory cells, each said array including a preselected number of primary cells and a preselected number of redundant memory cells; circuitry for preventing access to defective ones of said primary cells of a first selected one of said banks; and address decoding circuitry for accessing selected ones of said redundant cells in a second selected one of said banks in response to a redundancy address presented by said controller on said redundancy bus said redundancy address including a plurality of primary row/column address bits and at least one redundancy address bit; and wherein said controller is operable to generate said redundancy address to access said selected redundant cells in response to need to access said defective primary cells.

Claim 23

A processing system comprising: a controller; a redundancy bus; a memory comprising: a plurality of memory banks each comprising an array of memory cells, each said array including a preselected number of primary cells and a preselected number of redundant memory cells; circuitry for preventing access to defective ones of said primary cells of a first selected one of said banks; and address decoding circuitry for accessing selected ones of said redundant cells in a second selected one of said banks in response to a redundancy address presented by said controller on said redundancy bus said redundancy address including a plurality of primary row/column address bits and at least one redundancy address bit; and wherein said controller is operable to generate said redundancy address to access said selected redundant cells in response to need to access said defective primary cells.

Claim 24

The system of claim 20 wherein said controller and said memory are fabricated as a single chip integrated controller-memory device.

Claim 25

The system of claim 20 and further comprising a central processing unit coupled to said controller by a system bus.

Claim 26

The system of claim 20 wherein said defective primary cells are associated with an address and said controller generates said redundancy address by translating said address associated with said defective primary cells.

Claim 27

The system of claim 23 wherein said address associated with said defective primary cells comprises a plurality of row/column address bits and at least one bank select bit and said redundancy address comprises a plurality of row/column address bits, at least one bank select bit and at least one redundancy address bit.

Claim 30

The method of claim 25 wherein said step of addressing the redundant cells comprises the substep of translating the address associated with the defective cells to generate the address to the redundant set of cells.