US5287527A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logical signal output drivers for integrated circuit interconnection
Assignee: International Business Machines Corp
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Filing: 1992-12-28
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Granted: 1994-02-15
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Expires: 2012-12-28
Abstract
Abstract Disclosed is a logic output signal generating integrated circuit having a plurality of output drivers connected in parallel between a power bus and a ground bus. Each output driver has a pull up device disposed between the power bus and an output terminal and a pull down device disposed between the output terminal and the ground bus. Output drivers are paired for the reception of control signals. Control gates to the pull up device and the pull down device for one output driver in a pair is connected to receive an on-chip logic signal. The second output driver of the pair has the complement of that logic signal applied to the control gates of its pull up and pull down devices. An inverter operates on the logic signal to provide the complement. The load is divided between the output drivers for the true signals and those for the complementary signals.
Inventors
- 👤 Gary S. Delp
- 👤 Brian A. Schuelke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
130 words
A memory storage device comprising: first and second banks of integrated circuit storage devices; an address signal generator for providing an address and a complement of the address; a first logic bus connected between the address signal generator and the first bank of integrated storage devices for for applying the address to the first bank; a second logic bus connected between the address signal generator and the second bank of integrated storage devices for applying the complement of the address to the second bank; and a data bus for accessing a location in the first bank in response to application of the address and a location in the second bank in response to application of the complement of the address to read or write a dataword divided between the locations.
Claim 2
Dependent Claim
130 words
A memory storage device comprising: first and second banks of integrated circuit storage devices; an address signal generator for providing an address and a complement of the address; a first logic bus connected between the address signal generator and the first bank of integrated storage devices for for applying the address to the first bank; a second logic bus connected between the address signal generator and the second bank of integrated storage devices for applying the complement of the address to the second bank; and a data bus for accessing a location in the first bank in response to application of the address and a location in the second bank in response to application of the complement of the address to read or write a dataword divided between the locations.
Claim 3
Dependent Claim
68 words
A memory storage device as set forth in claim 1, and further comprising: an output driver on the address generator connected to each line in the first logic bus and the second logic bus; and wherein output drivers connected to lines in the first logic bus receive on chip address signals and output drivers connected to lines in the second logic bus receive inverted on chip address signals.
Claim 4
Dependent Claim
113 words
A memory storage device as set forth in claim 1, wherein the address signal generator is an integrated circuit and includes: a plurality of terminals for receiving on chip address signals; a plurality of inverters connected to the terminals for generating inverted on chip address signals; a power bus and a ground bus; and a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first address bus or the second address bus and a control input connected to one of the input terminals or to one of the plurality of inverters.
Claim 5
Dependent Claim
43 words
A memory storage device as set forth in claim 3, wherein each output driver further comprises: a pull up device connected between the power bus and the output terminal; and a pull down device connected between the output terminal and the ground bus.
Claim 6
Dependent Claim
26 words
A memory storage device as set forth in claim 4, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.
Claim 7
Dependent Claim
138 words
A data processing system comprising: a central processing unit; a system data bus connected to central processing unit; a system address bus connected to central processing unit; and first and second banks of integrated circuit storage devices; address signal processing logic connected between the system address bus and the first and second banks of integrated storage devices to apply an address over a first logic bus to the first bank of integrated storage devices and a complement of the address over a second logic bus to the second bank of integrated storage devices; and the system data bus accessing a location in the first bank in response to application of the address thereto and a location in the second bank in response to application of the complement of the address thereto to read or write a data word.
Claim 8
Dependent Claim
138 words
A data processing system comprising: a central processing unit; a system data bus connected to central processing unit; a system address bus connected to central processing unit; and first and second banks of integrated circuit storage devices; address signal processing logic connected between the system address bus and the first and second banks of integrated storage devices to apply an address over a first logic bus to the first bank of integrated storage devices and a complement of the address over a second logic bus to the second bank of integrated storage devices; and the system data bus accessing a location in the first bank in response to application of the address thereto and a location in the second bank in response to application of the complement of the address thereto to read or write a data word.
Claim 9
Dependent Claim
63 words
A data processing system as set forth in claim 6, and further comprising: an output driver for each line in the first logic bus and the second logic bus; wherein the output drivers connected to lines in the first logic bus receive on chip address signals and output drivers connected to lines in the second logic bus receive inverted on chip address signals.
Claim 10
Dependent Claim
110 words
A data processing system as set forth in claim 7, wherein the address signal processing logic further includes: a plurality of terminals for receiving on chip address signals; a plurality of inverters connected to the terminals for generating inverted on chip address signals; a power bus and a ground bus; and a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first address bus or the second address bus and a control input connected to one of the input terminals or to one of the plurality of inverters.
Claim 11
Dependent Claim
43 words
A data processing system as set forth in claim 8, wherein each output driver further comprises: a pull up device connected between the power bus and the output terminal; and a pull down device connected between the output terminal and the ground bus.
Claim 12
Dependent Claim
26 words
A data processing system as set forth in claim 9, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.
Claim 13
Dependent Claim
109 words
A memory storage device comprising: first and second banks of integrated circuit storage; an address signal generator; a first logic bus connected to the first bank of integrated circuit storage; a second logic bus connected to the second bank of integrated circuit storage; a power bus and a ground bus; a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first logic bus or the second logic bus and a control input connected to one of the input terminals or to one of the plurality of inverters.
Claim 14
Dependent Claim
109 words
A memory storage device comprising: first and second banks of integrated circuit storage; an address signal generator; a first logic bus connected to the first bank of integrated circuit storage; a second logic bus connected to the second bank of integrated circuit storage; a power bus and a ground bus; a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first logic bus or the second logic bus and a control input connected to one of the input terminals or to one of the plurality of inverters.
Claim 15
Dependent Claim
43 words
A memory storage device as set forth in claim 11, wherein each output driver further comprises: a pull up device connected between the power bus and the output terminal; and a pull down device connected between the output terminal and the ground bus.
Claim 16
Dependent Claim
26 words
A memory storage device as set forth in claim 12, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |