US5469388A
Expired / Lapsed
US
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Row redundancy circuit suitable for high density semiconductor memory devices
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-11-23
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Granted: 1995-11-21
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Expires: 2013-11-23
Abstract
Abstract A semiconductor memory device has a plurality of memory cell arrays, each with a normal cell array and a spare cell array. Fuse circuits are programmable to substitute a spare-cell-array word line for a defective word line in any normal cell array. When a defective word line is addressed, a fuse circuit activates a spare-cell-array word line, and also activates a redundancy signal line. A single redundancy signal line is shared by all fuse circuits and block select circuits. Block select circuits normally enable the cell array that includes the defective word line, however, the block select circuits are disabled when the defective word line has been replaced by a spare word line an another block.
Inventors
- 👤 Chan-Jong Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:56
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/808; G11C29/781
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
82 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; and a row redundancy circuit that is programmable to substitute a row in a spare cell array for a defective row in any normal cell array responsive to a single redundancy enable signal supplied to each of said plurality of memory cell arrays through a single bus line.
Claim 2
Dependent Claim
82 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; and a row redundancy circuit that is programmable to substitute a row in a spare cell array for a defective row in any normal cell array responsive to a single redundancy enable signal supplied to each of said plurality of memory cell arrays through a single bus line.
Claim 3
Dependent Claim
64 words
The memory of claim 1 wherein the row redundancy circuit comprises: a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array; and a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in said normal cell array.
Claim 4
Dependent Claim
52 words
The memory of claim 1 wherein the row redundancy circuit comprises: a plurality of block select circuits, each enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.
Claim 5
Dependent Claim
122 words
The memory of claim 1 wherein the row redundancy circuit comprises: a plurality of fuse circuits, each associated with a memory cell array and programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits, each associated with a memory cell array and a fuse circuit, each enabling its associated cell array when an addressed word line is in the associated cell array, except when the redundancy signal is activated by a fuse circuit other than its associated fuse circuit.
Claim 6
Dependent Claim
105 words
The memory of claim 1 wherein the row redundancy circuit comprises: a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits, each enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.
Claim 7
Dependent Claim
18 words
The semiconductor memory device of claim 1, wherein said single bus line is arranged in a peripheral circuit.
Claim 8
Dependent Claim
152 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits enabled by a redundancy enable signal provided to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.
Claim 9
Dependent Claim
152 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits enabled by a redundancy enable signal provided to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.
Claim 10
Dependent Claim
18 words
The semiconductor memory device of claim 7, wherein said single bus line is arranged in a peripheral circuit.
Claim 11
Dependent Claim
173 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; a plurality of fuse circuits, each associated with a memory cell array and programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits, each associated with a memory cell array and a fuse circuit and enabled by a redundancy enable circuit supplied to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling its associated cell array when an addressed word line is in its associated cell array, except when the redundancy signal is activated by a fuse circuit with which the block select circuit is not associated.
Claim 12
Dependent Claim
173 words
A semiconductor memory device comprising: a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array; a plurality of decoders for addressing memory cell arrays; a plurality of fuse circuits, each associated with a memory cell array and programmable to substitute a spare word line for a defective word line in any normal cell array; a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and a plurality of block select circuits, each associated with a memory cell array and a fuse circuit and enabled by a redundancy enable circuit supplied to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling its associated cell array when an addressed word line is in its associated cell array, except when the redundancy signal is activated by a fuse circuit with which the block select circuit is not associated.
Claim 13
Dependent Claim
18 words
The semiconductor memory device of claim 9, wherein said single bus line is arranged in a peripheral circuit.
References Cited (Backward Citations)
US5265055A
Cited
US5257229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |