US5701029A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor having polycrystalline silicon sandwiched by semiconductor substrate and metal silicide
Assignee: NEC Corp
•
Filing: 1995-09-28
•
Granted: 1997-12-23
•
Expires: 2015-09-28
Abstract
Abstract In a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer, a transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.
Inventors
- 👤 Masakazu Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:37
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/0113; H10D64/20; H10D64/23; H10D64/231; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
169 words
A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, a first level portion of said polycrystalline silicon layer at a bottom of said opening and a second level portion of said polycrystalline silicon layer at a surface of said insulating layer each having a thickness which is smaller than a transverse thickness of a third portion of said polycrystalline silicon layer at a sidewall of said insulating layer between said first level and second level portions; and a metal silicide layer formed on said polycrystalline silicon layer, wherein a crystal grain size of said polycrystalline silicon layer around the sidewall of said insulating layer is larger than a crystal grain size of said polycrystalline silicon layer around said impurity doped region and the surface of said insulating layer.
Claim 2
Dependent Claim
169 words
A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, a first level portion of said polycrystalline silicon layer at a bottom of said opening and a second level portion of said polycrystalline silicon layer at a surface of said insulating layer each having a thickness which is smaller than a transverse thickness of a third portion of said polycrystalline silicon layer at a sidewall of said insulating layer between said first level and second level portions; and a metal silicide layer formed on said polycrystalline silicon layer, wherein a crystal grain size of said polycrystalline silicon layer around the sidewall of said insulating layer is larger than a crystal grain size of said polycrystalline silicon layer around said impurity doped region and the surface of said insulating layer.
Claim 3
Dependent Claim
24 words
A device as set forth in claim 1, wherein said impurity doped region is formed in self-alignment with the opening of said insulating layer.
Claim 4
Dependent Claim
19 words
A device as set forth in claim 1, further comprising a metal layer formed on said polycrystalline silicon layer.
Claim 5
Dependent Claim
25 words
A device as set forth in claim 3, further comprising a high melting point metal layer between said metal silicide layer and said metal layer.
Claim 6
Dependent Claim
51 words
A device as set forth in claim 1, wherein said polycrystalline silicon layer comprises: a first polycrystalline silicon layer formed on the sidewall of said insulating layer; and a second polycrystalline silicon layer formed on the surface of said insulating layer, said first polycrystalline silicon layer and said impurity doped region.
Claim 7
Dependent Claim
93 words
A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, said polycrystalline silicon layer having a larger crystal grain size at a sidewall of said insulating layer than at a bottom of said opening and at a surface of said insulating layer; and a metal silicide layer formed on said polycrystalline silicon layer.
Claim 8
Dependent Claim
93 words
A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, said polycrystalline silicon layer having a larger crystal grain size at a sidewall of said insulating layer than at a bottom of said opening and at a surface of said insulating layer; and a metal silicide layer formed on said polycrystalline silicon layer.
Claim 9
Dependent Claim
24 words
A device as set forth in claim 6, wherein said impurity doped region is formed in self-alignment with the opening of said insulating layer.
Claim 10
Dependent Claim
19 words
A device as set forth in claim 6, further comprising a metal layer formed on said polycrystalline silicon layer.
Claim 11
Dependent Claim
25 words
A device as set forth in claim 8, further comprising a high melting point metal layer between said metal silicide layer and said metal layer.
Claim 12
Dependent Claim
51 words
A device as set forth in claim 6, wherein said polycrystalline silicon layer comprises: a first polycrystalline silicon layer formed on the sidewall of said insulating layer; and a second polycrystalline silicon layer formed on the surface of said insulating layer, said first polycrystalline silicon layer and said impurity doped region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |