Method of forming an MNOS/MONOS by employing large tilt angle ion implantation underneath the field oxide

Claim 1

The method of forming an MNOS/MONOS FET device with constant threshold voltage, the method comprising: forming a silicon oxide layer on the surface of a semiconductor substrate; depositing a layer of silicon nitride over said silicon oxide layer and patterning said silicon nitride layer; performing ion implantation at a tilt angle to form channel stop regions in said semiconductor substrate not covered by said patterned silicon nitride layer wherein said channel stop regions partially extend underneath said patterned silicon nitride layer; oxidizing said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate wherein each of said field oxide regions has a bird's beak at the portions of said semiconductor substrate underlying edges of said patterned silicon nitride layer and wherein said channel stop regions extend under a full length of said field oxide regions and under said bird's beaks; removing said patterned silicon nitride layer; providing an insulating layer over a surface of said semiconductor substrate, said insulating layer including an oxide layer formed on said surface of said semiconductor substrate and a nitride layer formed on said oxide layer; depositing a layer of polysilicon overlying said insulating layer and patterning said polysilicon layer to define a gate electrode extending over said surface of said semiconductor substrate, over said bird's beaks and over portions of said channel stop regions; and forming source and drain regions within said semiconductor substrate to provide said MNOS/MONOS FET device with a constant threshold voltage.

Claim 2

The method of forming an MNOS/MONOS FET device with constant threshold voltage, the method comprising: forming a silicon oxide layer on the surface of a semiconductor substrate; depositing a layer of silicon nitride over said silicon oxide layer and patterning said silicon nitride layer; performing ion implantation at a tilt angle to form channel stop regions in said semiconductor substrate not covered by said patterned silicon nitride layer wherein said channel stop regions partially extend underneath said patterned silicon nitride layer; oxidizing said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate wherein each of said field oxide regions has a bird's beak at the portions of said semiconductor substrate underlying edges of said patterned silicon nitride layer and wherein said channel stop regions extend under a full length of said field oxide regions and under said bird's beaks; removing said patterned silicon nitride layer; providing an insulating layer over a surface of said semiconductor substrate, said insulating layer including an oxide layer formed on said surface of said semiconductor substrate and a nitride layer formed on said oxide layer; depositing a layer of polysilicon overlying said insulating layer and patterning said polysilicon layer to define a gate electrode extending over said surface of said semiconductor substrate, over said bird's beaks and over portions of said channel stop regions; and forming source and drain regions within said semiconductor substrate to provide said MNOS/MONOS FET device with a constant threshold voltage.

Claim 12

The method of forming an EEPROM device with a constant threshold voltage, the method comprising: forming a silicon oxide layer on the surface of a semiconductor substrate; depositing a layer of silicon nitride over said silicon oxide layer and patterning said silicon nitride layer; performing ion implantation at a tilt angle of between about 10° to 70° to form channel stop regions in said semiconductor substrate not covered by said patterned silicon nitride layer wherein said channel stop regions partially extend underneath said patterned silicon nitride layer; oxidizing said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate wherein each of said field oxide regions has a bird's beak at the portions of said semiconductor substrate underlying edges of said patterned silicon nitride layer and wherein said channel stop regions extend under a full length of said field oxide regions and under said bird's beaks; removing said patterned silicon nitride layer; providing an insulating layer over a surface of said semiconductor substrate, said insulating layer including an oxide layer formed on said surface of said semiconductor substrate and a nitride layer formed on said oxide layer; depositing a layer of polysilicon overlying said insulating layer and patterning said polysilicon layer to define a gate electrode extending over said surface of said semiconductor substrate, over said bird's beaks and over portions of said channel stop regions; and forming source and drain regions within said semiconductor substrate to provide said EEPROM device with a constant threshold voltage over said gate electrode.

Claim 13

The method of forming an EEPROM device with a constant threshold voltage, the method comprising: forming a silicon oxide layer on the surface of a semiconductor substrate; depositing a layer of silicon nitride over said silicon oxide layer and patterning said silicon nitride layer; performing ion implantation at a tilt angle of between about 10° to 70° to form channel stop regions in said semiconductor substrate not covered by said patterned silicon nitride layer wherein said channel stop regions partially extend underneath said patterned silicon nitride layer; oxidizing said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate not covered by said patterned silicon nitride layer to form field oxide regions within said semiconductor substrate wherein each of said field oxide regions has a bird's beak at the portions of said semiconductor substrate underlying edges of said patterned silicon nitride layer and wherein said channel stop regions extend under a full length of said field oxide regions and under said bird's beaks; removing said patterned silicon nitride layer; providing an insulating layer over a surface of said semiconductor substrate, said insulating layer including an oxide layer formed on said surface of said semiconductor substrate and a nitride layer formed on said oxide layer; depositing a layer of polysilicon overlying said insulating layer and patterning said polysilicon layer to define a gate electrode extending over said surface of said semiconductor substrate, over said bird's beaks and over portions of said channel stop regions; and forming source and drain regions within said semiconductor substrate to provide said EEPROM device with a constant threshold voltage over said gate electrode.