US5700716A
Expired / Lapsed
US
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Method for forming low contact resistance contacts, vias, and plugs with diffusion barriers
Assignee: Micron Technology Inc
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Filing: 1996-02-23
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Granted: 1997-12-23
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Expires: 2016-02-23
Abstract
Abstract Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.
Inventors
- 👤 Sujit Sharan
- 👤 Varatharajan Nagabushnam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:43
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/047; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/01125; H10D64/0113; H10D64/025; H10W20/033; H10W20/048; H10W20/056; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
99 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit wafer, the method comprising the steps of: forming a contact opening through an insulating layer above the semiconductor device, wherein the contact opening defines a sidewall in the insulating layer; forming a layer of titanium in the bottom of the contact opening; forming a layer of polysilicon over the titanium layer in the contact opening, the polysilicon layer being doped, whereby the layer of polysilicon contacts the sidewall in the insulating layer; and annealing the in-process integrated circuit wafer.
Claim 2
Independent Claim
99 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit wafer, the method comprising the steps of: forming a contact opening through an insulating layer above the semiconductor device, wherein the contact opening defines a sidewall in the insulating layer; forming a layer of titanium in the bottom of the contact opening; forming a layer of polysilicon over the titanium layer in the contact opening, the polysilicon layer being doped, whereby the layer of polysilicon contacts the sidewall in the insulating layer; and annealing the in-process integrated circuit wafer.
Claim 3
Dependent Claim
73 words
A method as recited in claim 1, wherein the step of annealing the in-process integrated circuit wafer results in the formation of a structure in the contact opening which comprises: a titanium silicide layer located in the bottom of the contact opening; a titanium boride layer located above the titanium silicide layer in the contact opening; and a polysilicon layer substantially filling the remainder of the contact opening, the polysilicon layer being doped.
Claim 4
Dependent Claim
36 words
A method as recited in claim 1, wherein the contact opening defines a sidewall in the insulating layer, the insulating layer comprising oxide, and wherein the polysilicon layer substantially adheres to the oxide of the sidewall.
Claim 5
Dependent Claim
21 words
A method as recited in claim 1, wherein the titanium layer is deposited in the contact opening by chemical vapor deposition.
Claim 6
Dependent Claim
27 words
A method as recited in claim 1, wherein the titanium layer is formed with a thickness in a range of about 200 Angstroms to about 300 Angstroms.
Claim 7
Dependent Claim
27 words
A method as recited in claim 1, wherein the polysilicon layer is formed with a thickness in a range of about 6000 Angstroms to about 7000 Angstroms.
Claim 8
Dependent Claim
32 words
A method as recited in claim 1, wherein the polysilicon layer is doped with a range of about 1×10 20 to about 5×10 20 atoms of boron per cubic centimeter of polysilicon.
Claim 9
Dependent Claim
52 words
A method as recited in claim 1, wherein the step of annealing the in-process integrated circuit wafer comprises conducting a rapid thermal anneal in a rapid thermal processing chamber at a temperature in a range of about 800° C. to about 950° C. and for a time period of about 20 seconds.
Claim 10
Dependent Claim
55 words
A method as recited in claim 1, wherein the step of annealing the in-process integrated circuit wafer comprises placing the in-process integrated circuit wafer in a tube furnace having a temperature in a range of about 800° C. to about 900° C. in a predominately argon atmosphere for a time period of approximately 30 minutes.
Claim 11
Dependent Claim
17 words
A method as recited in claim 1, wherein the polysilicon layer is formed from a silane precursor.
Claim 12
Dependent Claim
55 words
A method as recited in claim 10, wherein the polysilicon layer is formed from the silane precursor in an atmosphere of B 2 H 6 , at a temperature in a range of about 630° C. to about 650° C., a pressure of about 80 Torr, and for a time period of about 300 seconds.
Claim 13
Dependent Claim
17 words
A method as recited in claim 1, wherein the polysilicon layer is formed from a disilane precursor.
Claim 14
Dependent Claim
56 words
A method as recited in claim 12, wherein the polysilicon layer is formed from the disilane precursor in an atmosphere of B 2 H 6 , at a temperature in a range of about 550° C. to about 570° C., at a pressure of about 80 Torr, and for a time period of about 150 seconds.
Claim 15
Independent Claim
157 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit wafer, the method comprising the steps of: forming a contact opening through an oxide layer above the semiconductor device; forming a layer of titanium in the bottom of the contact opening, the titanium layer having a thickness in a range of about 200 Angstroms to about 300 Angstroms; forming a layer of polysilicon over the titanium layer, the polysilicon layer having a thickness in a range of about 6000 to about 7000 Angstroms, the polysilicon layer being doped in a concentration range of about 1×10 20 to about 5×10 20 atoms of boron per cubic centimeter of polysilicon; and annealing the in-process integrated circuit wafer with a rapid thermal anneal in a rapid thermal processing chamber at a temperature range of about 900° C. to about 950° C. and for a time period of approximately 20 seconds.
Claim 16
Independent Claim
157 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit wafer, the method comprising the steps of: forming a contact opening through an oxide layer above the semiconductor device; forming a layer of titanium in the bottom of the contact opening, the titanium layer having a thickness in a range of about 200 Angstroms to about 300 Angstroms; forming a layer of polysilicon over the titanium layer, the polysilicon layer having a thickness in a range of about 6000 to about 7000 Angstroms, the polysilicon layer being doped in a concentration range of about 1×10 20 to about 5×10 20 atoms of boron per cubic centimeter of polysilicon; and annealing the in-process integrated circuit wafer with a rapid thermal anneal in a rapid thermal processing chamber at a temperature range of about 900° C. to about 950° C. and for a time period of approximately 20 seconds.
Claim 17
Dependent Claim
111 words
A method as recited in claim 14, wherein the step of annealing the in-process integrated circuit wafer results in the formation of a contact structure in the contact opening which comprises: a titanium silicide layer in the bottom of the contact opening, the titanium silicide layer having a thickness of approximately 200 Angstroms; a titanium boride layer located above the titanium silicide layer in the contact opening, the titanium boride layer having a thickness of approximately 250 Angstroms; and a polysilicon layer substantially filling the remainder of the contact opening, the polysilicon layer having a thickness in a range of about 6000 to about 7000 Angstroms, the polysilicon layer being doped.
Claim 18
Independent Claim
109 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit substrate, the method comprising: forming a contact opening through an insulating layer above the semiconductor device, wherein the contact opening has a bottom and defines a sidewall in the insulating layer, the insulating layer comprising oxide; forming a layer of titanium in the bottom of the contact opening; forming a layer of polysilicon over the titanium layer in the contact opening, the polysilicon layer being doped and wherein the polysilicon layer adheres to the oxide of the sidewall in the insulating layer; and annealing the in-process integrated circuit substrate.
Claim 19
Independent Claim
109 words
A method of forming a contact structure to provide electrical communication to a semiconductor device on an in-process integrated circuit substrate, the method comprising: forming a contact opening through an insulating layer above the semiconductor device, wherein the contact opening has a bottom and defines a sidewall in the insulating layer, the insulating layer comprising oxide; forming a layer of titanium in the bottom of the contact opening; forming a layer of polysilicon over the titanium layer in the contact opening, the polysilicon layer being doped and wherein the polysilicon layer adheres to the oxide of the sidewall in the insulating layer; and annealing the in-process integrated circuit substrate.
Claim 20
Dependent Claim
27 words
A method as recited in claim 16, wherein the titanium layer is formed with a thickness in a range of about 200 Angstroms to about 300 Angstroms.
Claim 21
Dependent Claim
27 words
A method as recited in claim 16, wherein the polysilicon layer is formed with a thickness in a range of about 6000 Angstroms to about 7000 Angstroms.
Claim 22
Dependent Claim
32 words
A method as recited in claim 16, wherein the polysilicon layer is doped with a range of about 1×10 20 to about 5×10 20 atoms of boron per cubic centimeter of polysilicon.
Claim 23
Dependent Claim
52 words
A method as recited in claim 16, wherein the step of annealing the in-process integrated circuit wafer comprises conducting a rapid thermal anneal in a rapid thermal processing chamber at a temperature in a range of about 800° C. to about 950° C. and for a time period of about 20 seconds.
Claim 24
Dependent Claim
55 words
A method as recited in claim 16, wherein the step of annealing the in-process integrated circuit wafer comprises placing the in-process integrated circuit wafer in a tube furnace having a temperature in a range of about 800° C. to about 900° C. in a predominately argon atmosphere for a time period of approximately 30 minutes.
Claim 25
Dependent Claim
17 words
A method as recited in claim 16, wherein the polysilicon layer is formed from a silane precursor.
Claim 26
Dependent Claim
55 words
A method as recited in claim 22, wherein the polysilicon layer is formed from the silane precursor in an atmosphere of B 2 H 6 , at a temperature in a range of about 630° C. to about 650° C., a pressure of about 80 Torr, and for a time period of about 300 seconds.
Claim 27
Dependent Claim
17 words
A method as recited in claim 16, wherein the polysilicon layer is formed from a disilane precursor.
Claim 28
Dependent Claim
56 words
A method as recited in claim 24, wherein the polysilicon layer is formed from the disilane precursor in an atmosphere of B 2 H 6 , at a temperature in a range of about 550° C. to about 570° C., at a pressure of about 80 Torr, and for a time period of about 150 seconds.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |