Bus driver

Claim 2

A bus driver comprising: an input terminal for receiving an input signal, a plurality of first to m-th buffer circuits for receiving as input said input signal from said input terminal, wherein m is an integer larger than 1, a delay circuit for delaying the input signal from said input terminal by a predetermined time period and outputting the delayed input signal as a delay signal, an n-th buffer circuit for receiving as input said delay signal from said delay circuit, wherein n is an integer larger than m, a capacitive device for selectively receiving as input a predetermined combination of output signals from said first to m-th buffer circuits, and an output terminal for outputting a signal composed of an output of said capacitive device and an output signal of said n-th buffer circuit.

Claim 3

The bus driver as set forth in claim 1, wherein at least one of said first to m-th buffer circuits receives a first control signal for permitting or inhibiting output of said at least one of said first to m-th buffer circuits, said control signal selectively controlling the output signals of said first to m-th buffer circuits to provide a plurality of combinations of the output signals to said capacitive device.

Claim 4

The bus driver as set forth in claim 1, wherein first and second buffer circuits are provided as said first to m-th buffer circuits, a third buffer circuit is provided as said n-th buffer circuit, said second buffer circuit receiving a first control signal provided for permitting or inhibiting output of said second buffer circuit, wherein said capacitive device receives as input one of the output signal of said first buffer circuit and a signal composed of the output signals of said first and second buffer circuits, and wherein said output terminal outputs two types of signals, each having a different rise time and fall time, which are each composed of the output signal of said third buffer circuit and one of two kinds of output signals from said capacitive device.

Claim 5

The bus driver as set forth in claim 1, wherein first to third buffer circuits are provided as said first to m-th buffer circuits, a fourth buffer circuit is provided as said n-th buffer circuit, said first to third buffer circuits receiving a first control signal for permitting or inhibiting output of at least one of said first to m-th buffer circuits, wherein said capacitive device receives as input three types of signals comprising combinations of the output signals from said first to third buffer circuits, and wherein said output terminal outputs three types of signals, each having a different rise time and fall time, which are combinations of the output signal of said fourth buffer circuit and three kinds of output signals from said capacitive device.

Claim 6

A bus driver comprising: an input terminal for receiving an input signal, a plurality of first to m-th buffer circuits for receiving as input said input signal from said input terminal, wherein m is an integer larger than 1, a delay circuit for delaying the input signal from said input terminal by a predetermined time period and outputting the delayed input signal as a delay signal, an n-th buffer circuit for receiving as input said delay signal from said delay circuit, wherein n is an integer larger than m, a capacitive device for selectively receiving as input a signal composed of at least one of output signals of said first to m-th buffer circuits, and an output terminal for selectively outputting said signal composed of at least one of the output signals of said first to m-th buffer circuits or a signal composed of the output of said capacitive device and the output signal of said n-th buffer circuit.

Claim 7

A bus driver comprising: an input terminal for receiving an input signal, a plurality of first to m-th buffer circuits for receiving as input said input signal from said input terminal, wherein m is an integer larger than 1, a delay circuit for delaying the input signal from said input terminal by a predetermined time period and outputting the delayed input signal as a delay signal, an n-th buffer circuit for receiving as input said delay signal from said delay circuit, wherein n is an integer larger than m, a capacitive device for selectively receiving as input a signal composed of at least one of output signals of said first to m-th buffer circuits, and an output terminal for selectively outputting said signal composed of at least one of the output signals of said first to m-th buffer circuits or a signal composed of the output of said capacitive device and the output signal of said n-th buffer circuit.

Claim 8

The bus driver as set forth in claim 5, wherein at least one of said first to m-th buffer circuits receives a first control signal for permitting or inhibiting output of said at least one of said first to m-th buffer circuits.

Claim 9

The bus driver as set forth in claim 5, further comprising: a selection circuit for selectively outputting said signal composed of at least one of the output signals of said first to m-th buffer circuits directly to one of said capacitive device and said output terminal.

Claim 10

The bus driver as set forth in claim 5, wherein at least one of said first to m-th buffer circuits receives a first control signal for permitting or inhibiting output of said at least one of said first to m-th buffer circuits, said control signal selectively controlling the output signals of said first to m-th buffer circuits to provide a plurality of combinations of the output signals to said capacitive device, said bus driver further comprising: a selection circuit for selectively outputting said signal composed of at least one of the output signals of said first to m-th buffer circuits directly to one of said capacitive device and said output terminal.

Claim 11

The bus driver as set forth in claim 5, further comprising: a selection circuit for selectively outputting said signal composed of at least one of the output signals of said first to m-th buffer circuits directly to one of said capacitive device and said output terminal, wherein said n-th buffer circuit receives a second control signal for inhibiting the output of said n-th buffer circuit when said selection circuit outputs the signal composed of at least one of the output signals of said first to m-th buffer circuits directly to said output terminal.

Claim 12

The bus driver as set forth in claim 5, wherein at least one of said first to m-th buffer circuits receives a first control signal for permitting or inhibiting output of said at least one of said first to m-th buffer circuits, said control signal selectively controlling the output signals of said first to m-th buffer circuits to provide a plurality of combinations of the output signals to said capacitive device, said bus driver further comprising: a selection circuit for selectively outputting a signal composed of at least one of the output signals of said first to m-th buffer circuits directly to one of said capacitive device and said output terminal, said n-th buffer circuit receiving a second control signal for inhibiting the outputs of said n-th buffer circuit when said selection circuit outputs the signal composed of the at least one of the output signals of said first to m-th buffer circuits directly to said output terminal.

Claim 13

The bus driver as set forth in claim 5, wherein first and second buffer circuits are provided as said first to m-th buffer circuits, and a third buffer circuit is provided as said n-th buffer circuit, said second buffer circuit receiving a first control signal provided for permitting or inhibiting output of said second buffer circuit, said bus driver further comprising: a selection circuit for selectively outputting a signal composed of at least one of the output signals of said first and second buffer circuits directly to one of said capacitive device and said output terminal, wherein said third buffer circuit receives a second control signal for inhibiting the output of said third buffer circuit when said selection circuit outputs said signal composed of at least one of the output signals of said first and second buffer circuits directly to said output terminal, wherein said capacitive device receives as input one of the output signal of said first buffer circuit and a signal composed of the output signals of said first and second buffer circuits, and wherein said output terminal outputs a plurality of types of signals, each having different rise times and fall times, including two types of signals which are each composed of the output signal of said third buffer circuit and one of two kinds of output signals from said capacitive device, and two types of signals which each include one of the output signal of said first buffer circuit and a signal composed of the output signals of said first and second buffer circuits.