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Patent US5696943A successfully refreshed from Google Patents.
US5696943A
Expired / Lapsed
US
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Method and apparatus for quick and reliable design modification on silicon
Assignee: Advanced Micro Devices Inc
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Filing: 1995-07-27
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Granted: 1997-12-09
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Expires: 2015-07-27
Abstract
Abstract In order to reduce product's time to market, a designer has to plan for debugging silicon before the first tape out. Having the proper type of spare gates at the desirable location will limit the number of new masks to three if not just one. Moreover, when these spare gates are easy to locate and are in the proper format, a FIB system can be used to debug the silicon and test the new fixes in real system environment before the next tape out. Thus, the spare gate strategy can limit the iteration of mask changes to just one, and this will speed up the time to market and bring higher profit from the product.
Inventors
- 👤 Dennis Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:12
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G06F2117/00; G06F2117/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
205 words
A method for effecting quickly and reliably design modifications on a silicon chip comprising the steps of: providing a plurality of spare gate sets, each set containing the types of standard spare cells most frequently used in the design; each of said plurality of spare gate sets including a combination of high-numbered input NAND logic gates, high-numbered input NOR logic gates, buffers, inverters, flip-flops, and glitch eater circuits; locating the plurality of spare gate sets to be near potential problem gates which are to be fixed or repaired; the locating step including the step of each of said plurality of spare gate sets with several different logic blocks on the silicon chip so that the plurality of spare gate sets will be spread throughout the layout of the silicon chip; formatting of the plurality of spare gate sets so as to be easily connectible to the potential problem gates without causing damage to other existing circuits on the silicon chip; the formatting step including the step connecting all of the inputs of the NAND logic gates to a positive power supply potential; and the formatting step further including the step of connecting all of the inputs of the NOR logic gates to a ground potential.
Claim 2
Independent Claim
205 words
A method for effecting quickly and reliably design modifications on a silicon chip comprising the steps of: providing a plurality of spare gate sets, each set containing the types of standard spare cells most frequently used in the design; each of said plurality of spare gate sets including a combination of high-numbered input NAND logic gates, high-numbered input NOR logic gates, buffers, inverters, flip-flops, and glitch eater circuits; locating the plurality of spare gate sets to be near potential problem gates which are to be fixed or repaired; the locating step including the step of each of said plurality of spare gate sets with several different logic blocks on the silicon chip so that the plurality of spare gate sets will be spread throughout the layout of the silicon chip; formatting of the plurality of spare gate sets so as to be easily connectible to the potential problem gates without causing damage to other existing circuits on the silicon chip; the formatting step including the step connecting all of the inputs of the NAND logic gates to a positive power supply potential; and the formatting step further including the step of connecting all of the inputs of the NOR logic gates to a ground potential.
Claim 3
Dependent Claim
28 words
A method as claimed in claim 1, further includes the step of utilizing a top-layer metal for making connections to the positive power supply potential or ground potential.
Claim 4
Dependent Claim
36 words
A method as claimed in claim 2, further comprising the step of providing metal lines for connecting the top-layer metal to the inputs of the NAND or NOR logic gates outside of the standard cell boundary.
Claim 5
Independent Claim
193 words
An apparatus for effecting quickly and reliably design modifications on a silicon chip comprising: disposing a plurality of spare gate sets on the silicon chip, each set being formed of the types of standard spare cells most frequently used in the design; said plurality of spare gate sets including a combination of high-numbered input NAND logic gates, high-numbered input NOR logic gates, buffers, inverters, flip-flops and glitch eater circuits; means for locating the plurality of spare gate sets to be near potential problem gates which are to be fixed or repaired; each of the plurality of spare gate sets being grouped with several different logic blocks on the silicon chip so that the plurality of spare gate sets will be spread throughout the layout of the silicon chip; means for formatting of the plurality of spare gate sets so as to be easily connectible to the potential problem gates without causing damage to other existing circuits on the silicon chip; all of the inputs of the NAND logic gates being connected to a positive power supply potential; and all of the inputs of the NOR logic gates being connected to a ground potential.
Claim 6
Independent Claim
193 words
An apparatus for effecting quickly and reliably design modifications on a silicon chip comprising: disposing a plurality of spare gate sets on the silicon chip, each set being formed of the types of standard spare cells most frequently used in the design; said plurality of spare gate sets including a combination of high-numbered input NAND logic gates, high-numbered input NOR logic gates, buffers, inverters, flip-flops and glitch eater circuits; means for locating the plurality of spare gate sets to be near potential problem gates which are to be fixed or repaired; each of the plurality of spare gate sets being grouped with several different logic blocks on the silicon chip so that the plurality of spare gate sets will be spread throughout the layout of the silicon chip; means for formatting of the plurality of spare gate sets so as to be easily connectible to the potential problem gates without causing damage to other existing circuits on the silicon chip; all of the inputs of the NAND logic gates being connected to a positive power supply potential; and all of the inputs of the NOR logic gates being connected to a ground potential.
Claim 7
Dependent Claim
26 words
An apparatus as claimed in claim 4, wherein a top-layer metal is provided for making the connections to the positive power supply potential or ground potential.
Claim 8
Dependent Claim
33 words
An apparatus as claimed in claim 5, wherein metal lines are provided for connecting the top-layer metal to the inputs of the NAND or NOR logic gates outside of the standard cell boundary.
References Cited (Backward Citations)
US4319396A
Cited
US4471472A
Cited
US4485459A
Cited
US4494220A
Cited
US4590388A
Cited
US5157618A
Cited
US4931946A
Cited
US5434868A
Cited
US5337318A
Cited
US5416740A
Cited
US5502333A
Cited
US5426379A
Cited
US5568067A
Cited
US5592107A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |