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US5696016A
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US
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Process for manufacturing a CMOSFET intergrated circuit
Assignee: Promos Technologies Inc
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Filing: 1996-11-15
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Granted: 1997-12-09
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Expires: 2016-11-15
Abstract
Abstract The present invention relates to a new process for fabricating integrated circuits, and more particularly, to a CMOS IC process method of low cost, shallow junction and no crystal defects. After the gate oxide and gate electrodes have been formed on the N-well and the P-well, an N - Lightly-Doped-Drain (N - LDD) is made, then the sidewall of the N-channel polysilicon gate and the P-channel polysilicon gate are covered with dielectric spacer. A layer of PhosphoSilicate Glass (PSG) is thereafter deposited and patterned on the N-well and the pickup area of the P-well by lithography and etching techniques. Ion implantation is used to build the P + Source/Drain (S/D) electrode, after which the sidewall spacer of the P-channel polysilicon gate is removed and a blanket implantation of P dopant forms the P - LDD on the area of the N-well. The P-well is doped with N-type dopant with its source from PSG by high temperature diffusing and forms the N + S/D electrode.
Inventors
- 👤 Ming-Liang Chen
- 👤 Chih-Hsun Chu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:50
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
179 words
A method for fabricating CMOSFET IC, comprising the steps of: forming N-well and P-well on a silicon substrate; adjusting threshold voltage by ion implantation; depositing gate oxide layer overlaying said silicon substrate; forming a P-channel FET gate and an N-channel FET gate over said silicon substrate; forming N - lightly doped drains (N - LDD) in said P-well not covered by said N-channel FET gate; forming dielectric sidewall spacers on said P-channel FET and N-channel FET gates; depositing and patterning Phosphosilicate glass (PSG) having phosphor dopants by lithography and etching to remove said PSG covering said N-well; forming P + source/drain regions in said N-well; removing said dielectric sidewall spacers of said P-channel FET gate; forming P - lightly doped drains (P - LDD) in said N-well; driving said phosphor dopants of said PSG into said P-well to form N + source/drain regions; forming a dielectric layer overlaying entire said silicon substrate and partially etching said dielectric layer to form a plurality of contact holes; and forming a metalization layer filling said contact holes and overlaying said dielectric layer.
Claim 2
Independent Claim
179 words
A method for fabricating CMOSFET IC, comprising the steps of: forming N-well and P-well on a silicon substrate; adjusting threshold voltage by ion implantation; depositing gate oxide layer overlaying said silicon substrate; forming a P-channel FET gate and an N-channel FET gate over said silicon substrate; forming N - lightly doped drains (N - LDD) in said P-well not covered by said N-channel FET gate; forming dielectric sidewall spacers on said P-channel FET and N-channel FET gates; depositing and patterning Phosphosilicate glass (PSG) having phosphor dopants by lithography and etching to remove said PSG covering said N-well; forming P + source/drain regions in said N-well; removing said dielectric sidewall spacers of said P-channel FET gate; forming P - lightly doped drains (P - LDD) in said N-well; driving said phosphor dopants of said PSG into said P-well to form N + source/drain regions; forming a dielectric layer overlaying entire said silicon substrate and partially etching said dielectric layer to form a plurality of contact holes; and forming a metalization layer filling said contact holes and overlaying said dielectric layer.
Claim 3
Dependent Claim
39 words
The method according to claim 1, wherein said N-well is formed by ion implanted arsenic (As 75 ) dopants, with an implantation dosage of 1E11 to 1E13 ions/cm 2 , and an implantation energy of 50 to 150 KeV.
Claim 4
Dependent Claim
39 words
The method according to claim 1, wherein said N-well is formed by ion implanted phosphorus (P 31 ) dopants, with an implantation dosage of 1E11 to 1E13 ions/cm 2 , and an implantation energy of 100 to 300 KeV.
Claim 5
Dependent Claim
39 words
The method according to claim 1, wherein said P-well is formed by ion implanted boron (B 11 ) dopants, with an implantation dosage of 1E12 to 1E13 ions/cm 2 , and an implantation energy of 20 to 80 KeV.
Claim 6
Dependent Claim
20 words
The method according to claim 1, wherein said gate oxide layer has a thickness of about 80 to 200 Angstroms.
Claim 7
Dependent Claim
28 words
The method according to claim 1, wherein said P-channel FET gate and said N-channel FET gate are formed by polysilicon with a thickness of 1000 to 4000 Angstroms.
Claim 8
Dependent Claim
42 words
The method according to claim 1, wherein said N - LDD is formed by an ion implanted arsenic (As 75 ) dopants, with an implantation dosage of 1E12 to 1E13 ions/cm 2 , and an implantation energy of 20 to 80 KeV.
Claim 9
Dependent Claim
27 words
The method according to claim 1, wherein said PSG with P 2 O 5 density ranges from 2 to 6%, and thickness from 3000 to 8000 Angstroms.
Claim 10
Dependent Claim
42 words
The method according to claim 1, wherein said P + source/drain is formed by employing a layer of Borosilicate glass (BSG) as a P-type dopant source wherein Boron dopants of said BSG are into said N-well to create said P + source/drain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |