Instruction breakpoint detection apparatus for use in an out-of-order microprocessor

Claim 2

An instruction breakpoint detection apparatus comprising: a memory element to store a linear breakpoint address; an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes; a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuit to compare said fetch instruction pointer to said linear breakpoint address; and a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction pointer and at least a portion of said linear breakpoint address.

Claim 3

The instruction breakpoint detection apparatus of claim 1 wherein instruction addresses comprise (T) total bits comprising (U) upper bits and (L) lower bits, the comparing circuit comprising circuitry to compare the upper (U) bits of the fetch instruction pointer with the upper (U) bits of the stored linear breakpoint address.

Claim 4

The instruction breakpoint apparatus of claim 2 wherein said byte marking circuit comprises an L:N decoding circuit to convert the lower (L) bits of the stored breakpoint address to said breakpoint marking sequence for marking said packet of aligned instruction data with a breakpoint bit which identifies said at least one byte as said code breakpoint.

Claim 5

The instruction breakpoint detection apparatus of claim 3 wherein said (T) total bits of (U) upper bits and (L) lower bits comprises 32 bits with 28 upper bits and 4 lower bits, said packet of aligned instruction data comprises 16 bytes, and said L:N decoding circuit comprises a 4:16 decoder.

Claim 6

The instruction breakpoint detection apparatus of claim 3 further comprising: an additional plurality of (M) memory elements to store a plurality of linear breakpoint addresses; and an additional plurality of (M) byte marking circuits, each associated with one of said additional plurality of memory elements, wherein said comparing circuit includes circuitry to compare said fetch instruction pointer to each of said plurality of linear breakpoint addresses.

Claim 7

The instruction breakpoint detection apparatus of claim 3 further including an instruction decoding mechanism to receive fetch instruction data, said instruction decoding mechanism including: detection circuitry to determine if the first byte of an instruction is marked with a breakpoint bit; and signaling circuitry to signal a breakpoint condition.

Claim 8

The instruction breakpoint detection apparatus of claim 5 wherein said breakpoint marking sequence includes only 1 bit for each byte of said packet of aligned instruction data.

Claim 9

The instruction breakpoint detection apparatus of claim 5 wherein said breakpoint marking sequence includes M bits for each byte of said packet of aligned instruction data.

Claim 10

A microprocessor comprising: an instruction execution block to execute instructions; an instruction fetch and decode block coupled to communicate with said instruction execution block, said instruction fetch and decoding block to fetch and decode instruction data for providing said instructions to said instruction execution block; and an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising: a memory element to store a linear breakpoint address; an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes; a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuitry to compare said fetch instruction pointer to said linear breakpoint address; and a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

Claim 11

A microprocessor comprising: an instruction execution block to execute instructions; an instruction fetch and decode block coupled to communicate with said instruction execution block, said instruction fetch and decoding block to fetch and decode instruction data for providing said instructions to said instruction execution block; and an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising: a memory element to store a linear breakpoint address; an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes; a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuitry to compare said fetch instruction pointer to said linear breakpoint address; and a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

Claim 12

The microprocessor of claim 9 wherein instruction addresses comprise (T) total bits comprising (U) upper bits and (L) lower bits, the comparing circuit comprising circuitry to compare the upper (U) bits of the fetch instruction pointer with the upper (U) bits of the stored linear breakpoint address.

Claim 13

The microprocessor of claim 10 wherein said byte marking circuit comprises an L:N decoding circuit to convert the lower (L) bits of the stored breakpoint address to said breakpoint marking sequence for marking said packet of aligned instruction data with a breakpoint bit which identifies said at least one byte as said code breakpoint.

Claim 14

The microprocessor of claim 11 wherein said (T) total bits of (U) upper bits and (L) lower bits comprises 32 bits with 28 upper bits and 4 lower bits, said packet of aligned instruction data comprises 16 bytes, and said L:N decoding circuit comprises a 4:16 decoder.

Claim 15

The microprocessor of claim 11 further comprising: an additional plurality of (M) memory elements to store a plurality of linear breakpoint addresses; and an additional plurality of (M) byte marking circuits, each associated with one of said additional plurality of memory elements, wherein said comparing circuit includes circuitry to compare said fetch instruction pointer to each of said plurality of linear breakpoint addresses.

Claim 16

The microprocessor of claim 11 further including an instruction decoding mechanism to receive fetch instruction data, said instruction decoding mechanism including: detection circuitry to determine if the first byte of an instruction is marked with a breakpoint bit; and signaling circuitry to signal a breakpoint condition.

Claim 17

The microprocessor of claim 13 wherein said breakpoint marking sequence includes only 1 bit for each byte of said packet of aligned instruction data.

Claim 18

The microprocessor of claim 13 wherein said breakpoint marking sequence includes M bits for each byte of said packet of aligned instruction data.

Claim 19

A computer system comprising: a bus; a main memory, coupled to said bus to store digital data; and a microprocessor, coupled to said bus, to process said digital data, said microprocessor comprising: an instruction fetch and decode block coupled to communicate with an execution block, said instruction fetch and decode block to fetch and decode instruction data for providing said instructions to said instruction execution block; and an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising: a memory element to store a linear breakpoint address; an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes; a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuit to compare said fetch instruction pointer to said linear breakpoint address; and a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

Claim 20

A computer system comprising: a bus; a main memory, coupled to said bus to store digital data; and a microprocessor, coupled to said bus, to process said digital data, said microprocessor comprising: an instruction fetch and decode block coupled to communicate with an execution block, said instruction fetch and decode block to fetch and decode instruction data for providing said instructions to said instruction execution block; and an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising: a memory element to store a linear breakpoint address; an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes; a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuit to compare said fetch instruction pointer to said linear breakpoint address; and a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

Claim 21

The computer system of claim 17 wherein instruction addresses comprise (T) total bits comprising (U) upper bits and (L) lower bits, the comparing circuit comprising circuitry to compare the upper (U) bits of the fetch instruction pointer with the upper (U) bits of the stored linear breakpoint address.

Claim 22

The computer system of claim 18 wherein said byte marking circuit comprises an L:N decoding circuit to convert the lower (L) bits of the stored breakpoint address to said breakpoint marking sequence for marking said packet of aligned instruction data with a breakpoint bit which identifies said at least one byte as said code breakpoint.

Claim 23

The computer system of claim 19 wherein said (T) total bits of (U) upper bits and (L) lower bits comprises 32 bits with 28 upper bits and 4 lower bits, said packet of aligned instruction data comprises 16 bytes, and said L:N decoding circuit comprises a 4:16 decoder.

Claim 24

The computer system of claim 19 further comprising: an additional plurality of (M) memory elements to store a plurality of linear breakpoint addresses; and an additional plurality of (M) byte marking circuits, each associated with one of said additional plurality of memory elements, wherein said comparing circuit includes circuitry to compare said fetch instruction pointer to each of said plurality of linear breakpoint addresses.

Claim 25

The computer system of claim 19 further including an instruction decoding mechanism for receiving fetch instruction data, said instruction decoding mechanism including: detection circuitry to determine if the first byte of an instruction is marked with a breakpoint bit; and signaling circuitry to signal a breakpoint condition.

Claim 26

The computer system of claim 21 wherein said breakpoint marking sequence includes only 1 bit for each byte of said packet of aligned instruction data.

Claim 27

The computer system of claim 21 wherein said breakpoint marking sequence includes M bits for each byte of said packet of aligned instruction data.

Claim 30

The method of claim 25 further comprising the step of signaling a breakpoint event if a first byte of an instruction is identified as the code breakpoint.

Claim 31

The method of claim 26 wherein said comparing step comprises the step of comparing said fetch instruction pointer with multiple stored breakpoint addresses.

Claim 32

The method of claim 26 wherein after said signaling step, said method comprises the step of determining which stored breakpoint address matched said fetch instruction pointer.

Claim 33

The method of claim 28 wherein sad comparing step comprises the step of comparing the upper bits of said breakpoint address with the upper bits of said fetch instruction pointer and said generating step comprises the steps of decoding the lower bits of said breakpoint address and appending said breakpoint marking sequence to said aligned packet.