US5479616A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception
Assignee: VIA Cyrix Inc
•
Filing: 1992-04-03
•
Granted: 1995-12-26
•
Expires: 2012-04-03
Abstract
Abstract An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit. When an invalid instruction byte is decoded, the decoder asserts a stall condition that can result from either: (a) the prefetch queue is invalid due to instruction bytes being unavailable or flushing in response to a branch, or (b) an exception condition. An exception processor (30) performs two basic functions: (a) monitoring the prefetch unit, and for any instruction byte for which a potential exception condition exists, storing in an exception status register the associated exception status information (for example, limit violation or page fault), and (b) monitoring the decoder to detect stall conditions. For each stall condition detected, the exception processor checks the exception status register for valid exception status information--if so, it invokes the appropriate exception handling routine. Thus, exception handling occurs at decode time, rather than after execution (requiring instruction abort and side effect handling).
Inventors
- 👤 Raul A. Garibay, Jr.
- 👤 Mark Bluhm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/3802
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
231 words
In a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, an exception handling system using the valid bits prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception comprising: prefetch logic including exception detection logic that determines, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, the prefetch logic stores the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and provides corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; and exception logic that monitors the prefetch logic, and stores exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, the exception logic detects the stall condition, and determines whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking the stored instruction status information; if the stall condition resulted from an exception condition, the exception logic causes an associated exception handling routine to be invoked.
Claim 2
Dependent Claim
231 words
In a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, an exception handling system using the valid bits prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception comprising: prefetch logic including exception detection logic that determines, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, the prefetch logic stores the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and provides corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; and exception logic that monitors the prefetch logic, and stores exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, the exception logic detects the stall condition, and determines whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking the stored instruction status information; if the stall condition resulted from an exception condition, the exception logic causes an associated exception handling routine to be invoked.
Claim 3
Dependent Claim
20 words
The exception handling system of claim 1, wherein the selected number of exception conditions includes page faults and limit violations.
Claim 4
Dependent Claim
17 words
The exception handling system of claim 1, wherein the exception logic invokes the exception handling routine directly.
Claim 5
Dependent Claim
21 words
The exception handling system of claim 1, wherein the exception logic includes an exception status register for storing exception status information.
Claim 6
Dependent Claim
203 words
For a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, a method of exception handling using the valid bits of prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception, comprising the steps: detecting, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, storing the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and providing corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; monitoring the exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, determining whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking associated instruction status information; and if the stall condition resulted from an exception condition, invoking an associated exception handling routine.
Claim 7
Dependent Claim
203 words
For a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, a method of exception handling using the valid bits of prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception, comprising the steps: detecting, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, storing the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and providing corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; monitoring the exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, determining whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking associated instruction status information; and if the stall condition resulted from an exception condition, invoking an associated exception handling routine.
Claim 8
Dependent Claim
20 words
The exception handling method of claim 5, wherein the selected number of exception conditions includes page faults and limit violations.
Claim 9
Dependent Claim
28 words
The exception handling method of claim 5, wherein the step of providing corresponding exception status information is accomplished by storing exception status information in an exception status register.
Claim 10
Dependent Claim
233 words
In a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, an exception handling system using the valid bits of prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception, comprising: prefetch means including exception detection means for determining, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, the prefetch means stores the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and provides corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; and exception means for monitoring the prefetch logic, and for storing exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, the exception means detects the stall condition, and determines whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking the stored instruction status information; if the stall condition resulted from an exception condition, the exception means causes an associated exception handling routine to be invoked.
Claim 11
Dependent Claim
233 words
In a processor including a prefetch unit for prefetching instruction bytes from a memory into a prefetch queue, where a valid bit is associated with each prefetched instruction byte in the prefetch queue such that, when that prefetched instruction byte is decoded, a stall condition will be signaled, an exception handling system using the valid bits of prefetched instruction bytes in the prefetch queue to identify instructions that will potentially cause an exception, comprising: prefetch means including exception detection means for determining, for prefetched instruction bytes, whether any of a selected number of exception conditions applies to any such prefetched instruction byte; if an exception condition is detected, the prefetch means stores the corresponding prefetched instruction byte in the prefetch queue with the valid bit for such prefetched instruction byte indicating that it is invalid, and provides corresponding exception status information identifying the exception condition associated with such prefetched instruction byte; and exception means for monitoring the prefetch logic, and for storing exception status information; in response to a stall condition signaled during decode of one of the prefetched instruction bytes, the exception means detects the stall condition, and determines whether that stall condition results from an exception condition associated with such prefetched instruction byte by checking the stored instruction status information; if the stall condition resulted from an exception condition, the exception means causes an associated exception handling routine to be invoked.
Claim 12
Dependent Claim
20 words
The exception handling system of claim 8, wherein the selected number of exception conditions includes page faults and limit violations.
Claim 13
Dependent Claim
18 words
The exception handling system of claim 8 , wherein the exception means invokes the exception handling routine directly.
Claim 14
Dependent Claim
21 words
The exception handling system of claim 8, wherein the exception means includes an exception status register for storing exception status information.
References Cited (Backward Citations)
US4747045A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |