US5694058A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic array integrated circuits with improved interconnection conductor utilization
Assignee: Altera Corp
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Filing: 1996-03-20
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Granted: 1997-12-02
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Expires: 2016-03-20
Abstract
Abstract In order to increase routing flexibility for the output signals of logic modules in programmable logic array integrated circuit devices, the output signal of each logic module can be swapped with the output signal of another logic module by a first level of signal swapping circuitry. The output signals of the first level of swapping circuitry can be further swapped with output signals of other first level swapping circuits by a second level of signal swapping circuitry to provide still more routing flexibility for the logic module output signals.
Inventors
- 👤 Srinivas T. Reddy
- 👤 Chiakang Sung
- 👤 Bonnie I-Keh Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1733; H03K19/1737; H03K19/17704; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
171 words
A programmable logic array integrated circuit device comprising: a plurality of regions of programmable logic, each being capable of producing an associated output signal, said regions being grouped in a plurality of pairs of said regions; a first signal swapping circuit associated with each of said pairs of logic regions, each of said first swapping circuits having two output terminals and being programmable to apply the output signal of either of the logic regions in the associated pair to either of said output terminals, said output terminals being grouped in a plurality of pairs of said output terminals such that the output terminals in each such pair are output terminals of different ones of said first swapping circuits; and a second signal swapping circuit associated with each of said pairs of output terminals, each of said second swapping circuits having two output leads and being programmable to connect either of the output terminals in the associated pair of output terminals to either of the output leads of said second swapping circuit.
Claim 2
Dependent Claim
171 words
A programmable logic array integrated circuit device comprising: a plurality of regions of programmable logic, each being capable of producing an associated output signal, said regions being grouped in a plurality of pairs of said regions; a first signal swapping circuit associated with each of said pairs of logic regions, each of said first swapping circuits having two output terminals and being programmable to apply the output signal of either of the logic regions in the associated pair to either of said output terminals, said output terminals being grouped in a plurality of pairs of said output terminals such that the output terminals in each such pair are output terminals of different ones of said first swapping circuits; and a second signal swapping circuit associated with each of said pairs of output terminals, each of said second swapping circuits having two output leads and being programmable to connect either of the output terminals in the associated pair of output terminals to either of the output leads of said second swapping circuit.
Claim 3
Dependent Claim
18 words
The apparatus defined in claim 1 wherein said pairs of said regions are mutually exclusive of one another.
Claim 4
Dependent Claim
19 words
The apparatus defined in claim 1 wherein said pairs of said output terminals are mutually exclusive of one another.
Claim 5
Dependent Claim
50 words
The apparatus defined in claim 1 further comprising: a plurality of interconnection conductors for use in making connections between various ones of said logic regions; and an output circuit associated with each of said output leads for connecting the associated output lead to a respective subset of said interconnection conductors.
Claim 6
Dependent Claim
31 words
The apparatus defined in claim 4 wherein each of said output circuits comprises: a driver circuit for selectively connecting the associated output lead to said respective subset of said interconnection conductors.
Claim 7
Dependent Claim
52 words
The apparatus defined in claim 1 wherein each of said pairs of said output terminals includes output terminals of a pair of said first signal swapping circuits, each of said pairs of said first signal swapping circuits being different from substantially all others of said pairs of said first signal swapping circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |