Configurable digital signal interface using field programmable gate array to reformat data

Claim 3

The apparatus of claim 1 further comprising: a second set of registers to store the second portions of the input signals; a second buffer to store a second combination of the second portions stored in the second set of registers, the second combination having the second data type; wherein the controller is configured to control transport of the second combination as the output signals from the second buffer to the memory of the computer system.

Claim 4

The apparatus of claim 2 further comprising: a first control command block to indicate a length, a status, and a destination address of the first combination.

Claim 5

The apparatus of claim 3 further comprising: a second control command block to indicate a length, a status, and a destination address of the second combination.

Claim 6

The apparatus of claim 4 including means for filling the second buffer with the second combination while transporting the first combination from the first buffer.

Claim 7

The apparatus of claim 2 wherein the first data type has a length of ten bits, and the second data type has a length of eight.

Claim 8

The apparatus of claim 2 wherein the input signals are received while the output signals are transported.

Claim 9

The apparatus of claim 7 wherein the source is a CCD camera producing ten bit pixels as input signals, and the second data type formats signals as eight bit bytes.

Claim 12

The apparatus of claim 9 wherein: the first transport channel includes a first set of registers and a first buffer configured to store the first portions of the input signals, and the second transport channel includes a second set of registers and a second buffer configured to store the second portions of the input signals, and further comprising a controller to control transport of the first portions from the first buffer to a memory of the computer system and transport of the second portions from the second buffer to the memory of the computer system.

Claim 13

The apparatus of claim 10 wherein the input data type is expressed in ten bits, the first output data type is expressed in eight bits, and the second output data type is expressed in two bits.

Claim 14

The apparatus of claim 10 wherein the input data type is expressed in twelve bits, the first output data type is expressed in eight bits, and the second output data type is expressed in four bits.

Claim 17

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a set of registers, each register in said set being configured to store a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length; a first buffer configured to receive first stored input signals having the second bit length in parallel from the set of registers and to store the received first stored input signals; a second buffer configured to receive second stored input signals having the second bit length in parallel from the set of registers and to store the received second stored input signals; and a controller configured to control the receipt of the first stored input signals by the first buffer and the second stored input signals by the second buffer, and to control transport of the received first stored input signals as output from the first buffer and the received second stored input signals as output from the second buffer to a memory of the computer system such that the transport of the received first stored input signals as output from the first buffer occurs simultaneous with receipt of the second stored input signals as input to the second buffer from the set of registers and the received first and the received second stored input signals are transported from the first and the second buffers as reformatted signals compatible with the computer system.

Claim 18

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a set of registers, each register in said set being configured to store a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length; a first buffer configured to receive first stored input signals having the second bit length in parallel from the set of registers and to store the received first stored input signals; a second buffer configured to receive second stored input signals having the second bit length in parallel from the set of registers and to store the received second stored input signals; and a controller configured to control the receipt of the first stored input signals by the first buffer and the second stored input signals by the second buffer, and to control transport of the received first stored input signals as output from the first buffer and the received second stored input signals as output from the second buffer to a memory of the computer system such that the transport of the received first stored input signals as output from the first buffer occurs simultaneous with receipt of the second stored input signals as input to the second buffer from the set of registers and the received first and the received second stored input signals are transported from the first and the second buffers as reformatted signals compatible with the computer system.

Claim 19

An interface according to claim 14, wherein the input signals are serial input signals and the second bit length is in a power of two increment of the first bit length.

Claim 20

An interface according to claim 14, further comprising: a null generator for generating null input signals, each null input signal having a third bit length; wherein each said register is configured to store the respective one of the input signals in combination with a respective one of the null input signals such that the total bit length of stored input signals in the set of registers equals the second bit length.

Claim 21

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a first set of registers, each register within said first set being configured to store a first portion of a respective one of the input signals such that a total bit length of stored first portions in the first set of registers equals the second bit length; a second set of registers, each register within said second set being configured to store a second portion of a respective one of the input signals, such that a total bit length of stored second portions in the second set of registers equals the second bit length; a first buffer configured to receive the stored first portions in parallel from the first set of registers and to store the received first portions; a second buffer configured to receive the stored second portions in parallel from the second set of registers and to store the received second portions; and a controller configured to control transport of the first portions as output from the first buffer to a memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system , the transported first and second portions being reformatted signals compatible with the computer system.

Claim 22

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a first set of registers, each register within said first set being configured to store a first portion of a respective one of the input signals such that a total bit length of stored first portions in the first set of registers equals the second bit length; a second set of registers, each register within said second set being configured to store a second portion of a respective one of the input signals, such that a total bit length of stored second portions in the second set of registers equals the second bit length; a first buffer configured to receive the stored first portions in parallel from the first set of registers and to store the received first portions; a second buffer configured to receive the stored second portions in parallel from the second set of registers and to store the received second portions; and a controller configured to control transport of the first portions as output from the first buffer to a memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system , the transported first and second portions being reformatted signals compatible with the computer system.

Claim 23

An interface according to claim 17, wherein the input signals are serial input signals and the second bit length is in a power of two increment of the first bit length.

Claim 24

An interface according to claim 17, wherein each first portion has a third bit length and each second portion has a fourth bit length and only the first, the third and the fourth bit lengths are expressible as a power of two number.

Claim 25

An interface according to claim 17, wherein the first set of registers includes a first number of registers and the second set of registers includes a second number of registers different than the first number of registers.

Claim 26

A field programmable gate array for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a set of registers, each register being selectively configurable to store (i), in a first programmed configuration, a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length and (ii) in a second programmed configuration, only a portion of a respective one of the input signals such that a total bit length of stored portions in the set of registers equals the second bit length, and thereby reformat the input signals to be compatible with the computer system; a first buffer configurable to (i), in the first programmed configuration, receive first stored input signals having the second bit length in parallel from the set of registers and to store the first stored input signals and (ii), in the second programmed configuration, to receive the stored first portions in parallel from the set of registers and to store the received first portions; a second buffer configurable (i), in the first programmed configuration, to receive second stored input signals having the second bit length in parallel from the set of registers and to store the second stored input signals and (ii), in the second programmed configuration, to receive second portions of the input signals from a second set of registers and to store the received second portions; and a controller configurable to control (i), in the a first programmed configuration, transport of the first stored input signals as output from the first buffer to a memory of the computer system and to control simultaneous receipt of the second stored input signals as input to the second buffer from the set of registers and (ii), in the second programmed configuration, transport of the first portions as output from the first buffer to the memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system.

Claim 27

A field programmable gate array for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising: a set of registers, each register being selectively configurable to store (i), in a first programmed configuration, a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length and (ii) in a second programmed configuration, only a portion of a respective one of the input signals such that a total bit length of stored portions in the set of registers equals the second bit length, and thereby reformat the input signals to be compatible with the computer system; a first buffer configurable to (i), in the first programmed configuration, receive first stored input signals having the second bit length in parallel from the set of registers and to store the first stored input signals and (ii), in the second programmed configuration, to receive the stored first portions in parallel from the set of registers and to store the received first portions; a second buffer configurable (i), in the first programmed configuration, to receive second stored input signals having the second bit length in parallel from the set of registers and to store the second stored input signals and (ii), in the second programmed configuration, to receive second portions of the input signals from a second set of registers and to store the received second portions; and a controller configurable to control (i), in the a first programmed configuration, transport of the first stored input signals as output from the first buffer to a memory of the computer system and to control simultaneous receipt of the second stored input signals as input to the second buffer from the set of registers and (ii), in the second programmed configuration, transport of the first portions as output from the first buffer to the memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system.