Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor

Claim 1

A non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, wherein each of the memory cell transistors comprises: first and second source/drain regions formed at a principal surface of a semiconductor substrate, separately from each other, to form a channel region between said first and second source/drain regions, said channel region being divided into a first channel region adjacent to said first source/drain region and a second channel region adjacent to said second source/drain region; a first gate insulator film formed on a surface of said first channel region; a first gate electrode formed on said first gate insulator film and having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said first source/drain region and a second side surface of said pair of opposite side surfaces being adjacent said second channel region; an insulator layer formed on a surface of each of said first and second source/drain regions; a second gate insulator film formed on an upper surface and said first and second side surfaces of said first gate electrode and on a surface of said second channel region; and a second gate electrode formed on said second gate insulator film and having opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively, wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

Claim 9

A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of: (a) forming a first gate electrode on a first gate insulator film formed on a principal surface of a semiconductor substrate; (b) forming first and second source/drain regions at said principal surface of said semiconductor substrate at opposite sides of said first gate electrode, in a self-alignment with said first gate electrode, so that a channel region is formed at said principal surface of said semiconductor substrate under said first gate electrode; (c) forming an insulator layer to cover a surface of said first and second source/drain regions; (d) removing an excess portion of said first gate electrode adjacent to said first source/drain region in a channel length direction, the remaining portion of said first gate electrode having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said second source/drain region and a second side surface of said pair of opposite side surfaces being opposite said first side surface; (e) forming a second gate insulator film on an upper surface and said first and second side surfaces of the remaining portion of said first gate electrode and on said principal surface of said semiconductor substrate from which said excess portion of said first gate electrode has been removed; and (f) forming a second gate electrode to cover said second gate insulator film and to have opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively, wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

Claim 10

A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of: (a) forming a first gate electrode on a first gate insulator film formed on a principal surface of a semiconductor substrate; (b) forming first and second source/drain regions at said principal surface of said semiconductor substrate at opposite sides of said first gate electrode, in a self-alignment with said first gate electrode, so that a channel region is formed at said principal surface of said semiconductor substrate under said first gate electrode; (c) forming an insulator layer to cover a surface of said first and second source/drain regions; (d) removing an excess portion of said first gate electrode adjacent to said first source/drain region in a channel length direction, the remaining portion of said first gate electrode having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said second source/drain region and a second side surface of said pair of opposite side surfaces being opposite said first side surface; (e) forming a second gate insulator film on an upper surface and said first and second side surfaces of the remaining portion of said first gate electrode and on said principal surface of said semiconductor substrate from which said excess portion of said first gate electrode has been removed; and (f) forming a second gate electrode to cover said second gate insulator film and to have opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively, wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

Claim 13

A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of: (a) forming on a principal surface of a semiconductor substrate a stacked layer structure composed of a first gate insulator film, a first gate electrode, a second gate insulator film and a first portion of a second gate electrode portion, stacked in the named order; (b) forming first and second source/drain regions at opposite sides of stacked layer structure, in a self-alignment with said stacked layer structure, so that a channel region is formed under said stacked layer structure; (c) forming an insulator layer to cover a surface of said first and second source/drain regions; (d) removing an excess portion of said stacked layer structure adjacent to said first source/drain region in a channel length direction; (e) forming a third gate insulator film on at least a side surface of a remaining portion of said stacked layer structure and said principal surface of said semiconductor substrate from which said excess portion of said stacked layer structure has been removed; (f) forming a second portion of said second gate electrode on said third gate insulator formed on said principal surface of said semiconductor substrate; (g) forming a third portion of said second gate electrode to cover said second portion of said second gate electrode and said first portion of said second gate electrode of said remaining portion of said stacked layer structure and to have opposite ends respectively terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

Claim 14

A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of: (a) forming on a principal surface of a semiconductor substrate a stacked layer structure composed of a first gate insulator film, a first gate electrode, a second gate insulator film and a first portion of a second gate electrode portion, stacked in the named order; (b) forming first and second source/drain regions at opposite sides of stacked layer structure, in a self-alignment with said stacked layer structure, so that a channel region is formed under said stacked layer structure; (c) forming an insulator layer to cover a surface of said first and second source/drain regions; (d) removing an excess portion of said stacked layer structure adjacent to said first source/drain region in a channel length direction; (e) forming a third gate insulator film on at least a side surface of a remaining portion of said stacked layer structure and said principal surface of said semiconductor substrate from which said excess portion of said stacked layer structure has been removed; (f) forming a second portion of said second gate electrode on said third gate insulator formed on said principal surface of said semiconductor substrate; (g) forming a third portion of said second gate electrode to cover said second portion of said second gate electrode and said first portion of said second gate electrode of said remaining portion of said stacked layer structure and to have opposite ends respectively terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.