SRAM cell having thin film transistors as loads

Claim 2

A static random access memory device comprising: first and second power supply lines; first and second connection plugs; a first load thin film transistor connected between said first power supply line and said first connection plug; a second load thin film transistor connected between said first power supply line and said second connection plug; a first driving MOS transistor connected between said first connection plug and said second power supply line; and a second driving MOS transistor connected between said second connection plug and said second power supply line, wherein said first connection plug is connected between a drain of said first load thin film transistor and said first driving MOS transistor such that said drain of said first load thin film transistor does not directly contact said first driving MOS transistor and wherein said first connection plug penetrates said drain of said first load thin film transistor, and wherein said second connection plug is connected between a drain of said second load thin film transistor and said second driving MOS transistor such that said drain of said second load thin film transistor does not directly contact said second driving MOS transistor and wherein said second connection plug penetrates the drain of said second load thin film transistor.

Claim 3

A device as set forth in claim 1, wherein said first and second connection plugs serve as first and second cross connection lines, respectively; said first cross connection line being between said drain of said first load thin film transistor and gates of said second load thin film transistor and said second driving MOS transistor; and said second cross connection line being between said drain of said second load thin film transistor and gates of said first load thin film transistor and said first driving MOS transistor.

Claim 4

A static random access memory device comprising: first and second power supply lines; first and second connection plugs; a first load thin film transistor connected between said first power supply line and said first connection plug; a second load thin film transistor connected between said first power supply line and said second connection plug; a first driving MOS transistor connected between said first connection plug and said second power supply line; a second driving MOS transistor connected between said second connection plug and said second power supply line; a first cross connection line between a drain of said first load thin film transistor and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between a drain of said second load thin film transistor and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and being electrically connected to said first and second connection plugs, respectively; first and second conductive layers formed above said semiconductor substrate and serving as source/channel/drain regions of said first and second load thin film transistors, respectively; wherein said first connection plug is connected between said first conductive layer and said first impurity region such that said drain of said first load thin film transistor does not directly contact said first impurity region and wherein said first connection plug penetrates said first conductive layer; and wherein said second connection plug is connected between said second conductive layer and said second impurity region such that said drain of said second load thin film transistor does not directly contact said second impurity region and wherein said second connection plug penetrates said second conductive layer.

Claim 5

A static random access memory device comprising: first and second power supply lines; first and second connection plugs; a first load thin film transistor connected between said first power supply line and said first connection plug; a second load thin film transistor connected between said first power supply line and said second connection plug; a first driving MOS transistor connected between said first connection plug and said second power supply line; a second driving MOS transistor connected between said second connection plug and said second power supply line; a first cross connection line between a drain of said first load thin film transistor and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between a drain of said second load thin film transistor and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and being electrically connected to said first and second connection plugs, respectively; first and second conductive layers formed above said semiconductor substrate and serving as source/channel/drain regions of said first and second load thin film transistors, respectively; wherein said first connection plug is connected between said first conductive layer and said first impurity region such that said drain of said first load thin film transistor does not directly contact said first impurity region and wherein said first connection plug penetrates said first conductive layer; and wherein said second connection plug is connected between said second conductive layer and said second impurity region such that said drain of said second load thin film transistor does not directly contact said second impurity region and wherein said second connection plug penetrates said second conductive layer.

Claim 6

A device as set forth in claim 3, wherein said first and second connection plugs serve as said first and second cross connection lings, respectively.

Claim 7

A static random access memory device comprising: first and second power supply lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node; a second load thin film transistor connected between said first power supply line and said second node; a first driving MOS transistor connected between said first node and said second power supply line; a second driving MOS transistor connected between said second node and said second power supply line; a first cross connection line between said first node and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between said second node and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and serving as said first and second nodes, respectively; first and second conductive layers formed above said semiconductor substrate and serving as gate electrodes of said first and second driving MOS transistors, respectively; third and fourth conductive layers formed above said first and second conductive layers and serving as source/channel/drain regions of said first and second thin film transistors, respectively; a first connection plug connected to said first impurity region and said second and third conductive layers, said first connection plug penetrating said second and third conductive layers; and a second connection plug connected to said second impurity region and said first and fourth conductive layers, said second connection plug penetrating said first and fourth conductive layers.

Claim 8

A static random access memory device comprising: first and second power supply lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node; a second load thin film transistor connected between said first power supply line and said second node; a first driving MOS transistor connected between said first node and said second power supply line; a second driving MOS transistor connected between said second node and said second power supply line; a first cross connection line between said first node and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between said second node and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and serving as said first and second nodes, respectively; first and second conductive layers formed above said semiconductor substrate and serving as gate electrodes of said first and second driving MOS transistors, respectively; third and fourth conductive layers formed above said first and second conductive layers and serving as source/channel/drain regions of said first and second thin film transistors, respectively; a first connection plug connected to said first impurity region and said second and third conductive layers, said first connection plug penetrating said second and third conductive layers; and a second connection plug connected to said second impurity region and said first and fourth conductive layers, said second connection plug penetrating said first and fourth conductive layers.

Claim 9

A device as set forth in claim 5, wherein said first and second connection plugs serve as said first and second cross connection lines, respectively.

Claim 10

A static random access memory device comprising: first and second power supply lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node; a second load thin film transistor connected between said first power supply line and said second node; a first driving MOS transistor connected between said first node and said second power supply line; a second driving MOS transistor connected between said second node and said second power supply line; a first cross connection line between said first node and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between said second node and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and serving as said first and second nodes, respectively; first and second conductive layers formed above said semiconductor substrate and serving as gate electrodes of said first and second driving MOS transistors, respectively; third and fourth conductive layers formed above said first and second conductive layers and serving as gate electrodes of said first and second thin film transistors, respectively; fifth and sixth conductive layers formed above said first and second conductive layers and serving as source/channel/drain regions of said first and second thin film transistors, respectively; a first connection plug connected to said first impurity region and said second, fourth and fifth conductive layers, said first connection plug penetrating said second, fourth and fifth conductive layers; and a second connection plug connected to said second impurity region and said first, third and sixth conductive layers, said second connection plug penetrating said first, third and sixth conductive layers.

Claim 11

A static random access memory device comprising: first and second power supply lines; first and second nodes; a first load thin film transistor connected between said first power supply line and said first node; a second load thin film transistor connected between said first power supply line and said second node; a first driving MOS transistor connected between said first node and said second power supply line; a second driving MOS transistor connected between said second node and said second power supply line; a first cross connection line between said first node and gates of said second load thin film transistor and said second driving MOS transistor; a second cross connection line between said second node and gates of said first load thin film transistor and said first driving MOS transistor; a semiconductor substrate of a first conductivity type; first and second impurity regions of a second conductivity type opposite said first conductivity type, said first and second impurity regions being formed within said semiconductor substrate and serving as said first and second nodes, respectively; first and second conductive layers formed above said semiconductor substrate and serving as gate electrodes of said first and second driving MOS transistors, respectively; third and fourth conductive layers formed above said first and second conductive layers and serving as gate electrodes of said first and second thin film transistors, respectively; fifth and sixth conductive layers formed above said first and second conductive layers and serving as source/channel/drain regions of said first and second thin film transistors, respectively; a first connection plug connected to said first impurity region and said second, fourth and fifth conductive layers, said first connection plug penetrating said second, fourth and fifth conductive layers; and a second connection plug connected to said second impurity region and said first, third and sixth conductive layers, said second connection plug penetrating said first, third and sixth conductive layers.

Claim 12

A device as set forth in claim 7, wherein said third and fourth conductive layers are beneath said fifth and sixth conductive layers.

Claim 13

A device as set forth in claim 7, wherein said third and fourth conductive layers are above said fifth and sixth conductive layers.

Claim 14

A device as set forth in claim 7, wherein said first and second connection plugs serve as said first and second cross connection lines, respectively.

Claim 15

The static random access memory as claimed in claim 1, wherein said first connection plug is connected between said drain of said first load thin film transistor and a drain of said first driving MOS transistor such that said drain of said first load thin film transistor does not directly contact said drain of said first driving MOS transistor, and wherein said second connection plug is connected between said drain of said second load thin film transistor and a drain of said second driving MOS transistor such that said drain of said second load thin film transistor does not directly contact said drain of said second driving MOS transistor.

Claim 16

The static random access memory as claimed in claim 11, wherein said first and second connection plugs serve as first and second cross connection lines, respectively; said first cross connection line being between said drain of said first load thin film transistor and gates of said second load thin film transistor and said second driving MOS transistor; said second cross connection line being between said drain of said second load thin film transistor and gates of said first load thin film transistor and said first driving MOS transistor; said gates of said second load thin film transistor and said second driving MOS transistor being connected to said first cross connection line such that said drain of said first load thin film transistor is not directly connected to said gates of said second load thin film transistor and said second driving MOS transistor; and said gates of said first load thin film transistor and said first driving MOS transistor being connected to said second cross connection line such that said drain of said second load thin film transistor is not directly connected to said gates of said first load thin film transistor and said first driving MOS transistor.

Claim 17

The static random access memory as claimed in claim 12, wherein said gates of said first load thin film transistor and said first driving MOS transistor are not directly connected to said drain of said second driving MOS transistor and wherein said gates of said second load thin film transistor and said second driving MOS transistor are not directly connected to said drain of said first driving MOS transistor.