EP0504006A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device having thin film transistor and method of producing the same
Assignee: Fujitsu Ltd
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Filing: 1992-03-03
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Granted: —
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Expires: 2012-03-03
Abstract
Abstract A semiconductor memory device includes a semiconductor substrate (1), a memory cell provided on the semiconductor substrate and including first and second transfer transistors (Q3, Q4), first and second driver transistors (Q1, Q2) and first and second thin film transistor loads (Q5, Q6), where each of the first and second transfer transistors, where the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected. The gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load are made of conductor layers which are stacked on the semiconductor substrate with an insulator layer interposed between the conductor layers, and a top one of the stacked conductor layers makes contact with a top surface of a bottom one of the stacked conductor layers and with side surfaces of each conductor layer provided between the top and bottom conductor layers within the connecting region.
Inventors
- 👤 Kazuo c/o FUJITSU LIMITED Itabashi
- 👤 Taiji C/O Fujitsu Limited Ema
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:20
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6729; H10D30/673; H10D30/6733; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
248 words
A semiconductor memory device comprising a semiconductor substrate (1); and a memory cell provided on the semiconductor substrate and including first and second transfer transistors (Q3, Q4), first and second driver transistors (Q1, Q2) and first and second thin film transistor loads (Q5, Q6), each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode, characterized in that there is provided: a connecting region (16A, 23A) in which the drain (18) of the second thin film transistor load (Q6), the gate electrode (15, 24) of the first thin film transistor load (Q5) and the gate electrode (4) of the first driver transistor (Q1) are connected; that the gate electrode (4) of the first driver transistor (Q1), the gate electrode (15, 24) of the first thin film transistor load (Q5) and the drain (18) of the second thin film transistor load (Q6) are made of conductor layers (4, 15, 18, 24) which are stacked on said semiconductor substrate (1) with an insulator layer (7, 9, 16, 23) interposed between the conductor layers; and that a top one (18, 24) of the stacked conductor layers (4, 15, 18, 24) makes contact with a top surface of a bottom one (4) of the stacked conductor layers and with side surfaces of each conductor layer (15, 18) provided between the top and bottom conductor layers within said connecting region (16A, 23A).
Claim 2
Dependent Claim
71 words
The semiconductor memory device as claimed in claim 1, characterized in that the top conductor layer (18) forms the drain (18) of the second thin film transistor load (Q6), the bottom conductor layer (4) forms the gate electrode (4) of the first driver transistor (Q1), and the conductor layer (15) provided between the top and bottom conductor layers forms the gate electrode (15) of the first thin film transistor load (Q5).
Claim 3
Dependent Claim
40 words
The semiconductor memory device as claimed in claim 2, characterized in that at least the conductor layers (15, 18) excluding the bottom conductor layer (4) are made of polysilicon, and the insulator layers (7, 9, 16) are made of SiO₂.
Claim 4
Dependent Claim
63 words
The semiconductor memory device as claimed in claim 3, characterized in that the bottom conductor layer (4) is made up of a first layer (4) formed on said semiconductor substrate (1) and a second layer (150) formed on the first layer (4), said second layer (150) being made of a material selected from a group consisting of refractory metals and refractory metal silicides.
Claim 5
Dependent Claim
67 words
The semiconductor memory device as claimed in any of claims 2 to 4, characterized in that the drain of the second driver transistor (Q2) is further connected to the gate electrode (4) of the first driver transistor (Q1), the gate electrode (15) of the first thin film transistor load (Q5) and the drain (18) of the second thin film transistor load (Q6) within said connecting region (16A).
Claim 6
Dependent Claim
79 words
The semiconductor memory device as claimed in claim 1, characterized in that the first thin film transistor load (Q5) has a channel region (19), and the gate electrode (15, 24) of the first thin film transistor load (Q5) is made up of a lower gate electrode (15) which is formed under the channel region (19) via an insulator layer (16) and an upper gate electrode (24) which is formed above the channel region (19) via an insulator layer (23).
Claim 7
Dependent Claim
87 words
The semiconductor memory device as claimed in claim 6, characterized in that the top conductor layer (24) forms the upper gate electrode (24) of the first thin film transistor load (Q5), the bottom conductor layer (4) forms the gate electrode (4) of the first driver transistor (Q1), and the conductor layers (18, 15) provided between the top and bottom conductor layers form the drain (18) of the second thin film transistor load (Q6) and the lower gate electrode (15) of the first thin film transistor load (Q5).
Claim 8
Dependent Claim
42 words
The semiconductor memory device as claimed in claim 7, characterized in that at least the conductor layers (15, 18, 24) excluding the bottom conductor layer (4) are made of polysilicon, and the insulator layers (7, 9, 16, 23) are made of SiO₂.
Claim 9
Dependent Claim
63 words
The semiconductor memory device as claimed in claim 8, characterized in that the bottom conductor layer (4) is made up of a first layer (4) formed on said semiconductor substrate (1) and a second layer (150) formed on the first layer (4), said second layer (150) being made of a material selected from a group consisting of refractory metals and refractory metal silicides.
Claim 10
Dependent Claim
68 words
The semiconductor memory device as claimed in any of claims 7 to 9, characterized in that the drain of the second driver transistor (Q2) is further connected to the gate electrode (4) of the first driver transistor (Q1), the gate electrode (15, 24) of the first thin film transistor load (Q5) and the drain (18) of the second thin film transistor load (Q6) within said connecting region (23A).
Claim 11
Independent Claim
201 words
A method of producing a semiconductor memory device which includes a memory cell made up of two transfer transistors (Q3, Q4), two driver transistors (Q1, Q2) and two thin film transistor loads (Q5, Q6), characterized in that said method comprises the steps of: (a) forming a gate insulator layer (3) on a semiconductor substrate (1) after forming a field insulator layer (2) on a surface of the semiconductor substrate; (b) forming a gate electrode (4) of the driver transistor (Q1) by forming a first conductor layer (4) and patterning the first conductor layer; (c) forming a first insulator layer (7) after forming impurity regions (5, 6) in the semiconductor substrate (1) using the field insulator layer (2) and the first conductor layer (4) as masks; (d) forming a second insulator layer (16) after forming and patterning a second conductor layer (15); (e) forming a corntact hole (16A) which extends from a top surface of the second insulator layer (16) and reaches a top surface of the first conductor layer (4); and (f) forming a third conductor layer (18) which makes contact with the top surface of the first conductor layer (4) and with side surfaces of the second conductor layer (15).
Claim 12
Dependent Claim
49 words
The method of producing the semiconductor memory device as claimed in claim 11, characterized in that said step (d) includes the substeps of: forming the second conductor layer (15); and patterning the second conductor layer (15) to form a gate electrode (15) of the thin film transistor load (Q5).
Claim 13
Dependent Claim
68 words
The method of producing the semiconductor memory device as claimed in claim 11 or 12, characterized in that said step (f) includes the substeps of: forming the third conductor layer (18) from a semiconductor; and selectively injecting impurities into the third conductor layer (18) to form a source region (17) and a drain region (18) which sandwich a channel region (19) of the thin film transistor load (Q6).
Claim 14
Independent Claim
44 words
The method of producing the semiconductor memory device as claimed in any of claims 11 to 13, characterized in that said steps (c) and (d) form the first and second insulator layers (7, 16) from SiO₂ and the second conductor layer (15) from polysilicon.
Claim 15
Dependent Claim
90 words
The method of producing the semiconductor memory device as claimed in claim 14, characterized in that said step (b) includes the substeps of: forming a first layer (4) which is made of a conductive material; and forming a second layer (150) which is made of a conductive material on the first layer (4) to form the first conductor layer which is made up of the first and second layers, said second layer (150) being made of a material selected from a group consisting of refractory metals and refractory metal silicides.
Claim 16
Dependent Claim
60 words
The method of producing the semiconductor memory device as claimed in claim 15, characterized in that said step (e) forms the contact hole (16A) by carrying out a reactive ion etching using CHF₃/He as an etching gas to remove the second and first insulator layers (16, 7) and HBr/Ar as an etching gas to remove the second conductor layer (15).
Claim 17
Dependent Claim
41 words
The method of producing the semiconductor memory device as claimed in claim 15 or 16, characterized in that said step (e) carries out an over-etching to form the contact hole (16A), so that no etching residue remains within the contact hole.
Claim 18
Independent Claim
220 words
A method of producing a semiconductor memory device which includes a memory cell made up of two transfer transistors (Q3, Q4), two driver transistors (Q1, Q2) and two thin film transistor loads (Q5, Q6), characterized in that said method comprises the steps of: (a) forming a gate insulator layer (3) on a semiconductor substrate (1) after forming a field insulator layer (2) on a surface of the semiconductor substrate; (b) forming a gate electrode (4) of the driver transistor (Q1) by forming a first conductor layer (4) and patterning the first conductor layer; (c) forming a first insulator layer (7) after forming impurity regions (5, 6) in the semiconductor substrate (1) using the field insulator layer (2) and the first conductor layer (4) as masks; (d) forming a second insulator layer (16) after forming and patterning a second conductor layer (15); (e) forming a third insulator layer (23) after forming and patterning a third conductor layer (18); (f) forming a contact hole (23A) which extends from a top surface of the third insulator layer (23) and reaches a top surface of the first conductor layer (4); and (g) forming a fourth conductor layer (24) which makes contact with the top surface of the first conductor layer (4) and with side surfaces of the second and third conductor layers (15, 18).
Claim 19
Dependent Claim
99 words
The method of producing the semiconductor memory device as claimed in claim 18, characterized in that said step (d) patterns the second conductor layer (15) to form a lower gate electrode (15) of the thin film transistor load (Q5), said step (e) selectively injects impurities into the third conductor layer (18) to form a source region (17) and a drain region (18) which sandwich a channel region (19) of the thin film transistor load (Q6), and said step (g) patterns the fourth conductor layer (24) to form an upper gate electrode (24) of the thin film transistor load (Q5).
Claim 20
Dependent Claim
48 words
The method of producing the semiconductor memory device as claimed in claim 18 or 19, characterized in that said steps (c), (d) and (e) form the first, second and third insulator layers (7, 16, 23) from SiO₂ and the second and third conductor layers (15, 18) from polysilicon.
Claim 21
Dependent Claim
90 words
The method of producing the semiconductor memory device as claimed in claim 20, characterized in that said step (b) includes the substeps of: forming a first layer (4) which is made of a conductive material; and forming a second layer (150) which is made of a conductive material on the first layer (4) to form the first conductor layer which is made up of the first and second layers, said second layer (150) being made of a material selected from a group consisting of refractory metals and refractory metal silicides.
Claim 22
Dependent Claim
65 words
The method of producing the semiconductor memory device as claimed in claim 21, characterized in that said step (f) forms the contact hole (23A) by carrying out a reactive ion etching using CHF₃/He as an etching gas to remove the third, second and first insulator layers (23, 16, 7) and HBr/Ar as an etching gas to remove the third and second conductor layers (18, 15).
Claim 23
Dependent Claim
39 words
The method of producing the semiconductor memory device as claimed in claim 21, characterized in that said step (f) carries out an over-etching to form the contact hole (23A), so that no etching residue remains within the contact hole.
References Cited (Backward Citations)
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