Patent US5684946A successfully refreshed from Google Patents.
US5684946A
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Apparatus and method for improving the efficiency and quality of functional verification
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-09-11
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Granted: 1997-11-04
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Expires: 2015-09-11
Abstract
Abstract A design verification system is provided which includes the ability to automatically correlate the response of a device under test to the input stimuli. The test system uses a pseudo-random exerciser to produce a set of test stimuli for application to a device under test. Once applied, the response of the device is recorded and an automatic correlation is performed using a chosen correlation engine. Once the correlation is complete a new set of stimuli is produced which results in improved test coverage for the device under test. The system is closed-loop and thus allows for iterative testing of a device under test.
Inventors
- 👤 James P. Ellis
- 👤 Mike Kantrowitz
- 👤 Will Sherwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:50
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
142 words
A design verification system comprising: test stimulus generator means for generating a plurality of input test stimuli for application to a device under test; application means for applying said test stimuli to said device under test; monitoring means for monitoring and recording responses of said device under test to said test stimuli and for monitoring occurrences of predetermined events resulting from said test stimuli; correlation means coupled to said monitoring means and said test stimulus generator means for analyzing said responses to determine cause and effect relationships between input parameters of said test stimulus generation means and said responses and for providing modified input parameters to said test stimulus generator means in order for said test stimulus generator means to generate, in a controlled fashion, a second different plurality of test stimuli for producing desired responses and occurrences of said predetermined events.
Claim 2
Dependent Claim
142 words
A design verification system comprising: test stimulus generator means for generating a plurality of input test stimuli for application to a device under test; application means for applying said test stimuli to said device under test; monitoring means for monitoring and recording responses of said device under test to said test stimuli and for monitoring occurrences of predetermined events resulting from said test stimuli; correlation means coupled to said monitoring means and said test stimulus generator means for analyzing said responses to determine cause and effect relationships between input parameters of said test stimulus generation means and said responses and for providing modified input parameters to said test stimulus generator means in order for said test stimulus generator means to generate, in a controlled fashion, a second different plurality of test stimuli for producing desired responses and occurrences of said predetermined events.
Claim 3
Dependent Claim
36 words
The system of claim 1 wherein said responses include internal signals of said device under test, values stored in queues of said device under test, and signal values at input/output pins of said device under test.
Claim 4
Dependent Claim
20 words
The system of claim 1 wherein said correlation means is a correlation engine based on Design Of Experiments (DOE) techniques.
Claim 5
Dependent Claim
18 words
The system of claim 3 wherein said correlation engine is a software program executed by a computer system.
Claim 6
Independent Claim
137 words
A method of verifying a circuit design comprising the steps of: a) generating, according to a set of parameters, a first set of test stimuli; b) applying said first set of test stimuli to a device under test; c) monitoring and recording responses of said device under test to said applied stimuli; d) correlating said responses with said applied stimuli to determine which input stimuli provide desired responses; e) modifying, based on said correlating step, said set of parameters associated with said generating step to provide parameters that produce said desired responses; f) generating, responsive to said modified set of parameters, a second set of test stimuli for providing increased test coverage; and g) repeating steps b through f until complete test coverage of said device under test is achieved and all desired responses have been produced.
Claim 7
Independent Claim
137 words
A method of verifying a circuit design comprising the steps of: a) generating, according to a set of parameters, a first set of test stimuli; b) applying said first set of test stimuli to a device under test; c) monitoring and recording responses of said device under test to said applied stimuli; d) correlating said responses with said applied stimuli to determine which input stimuli provide desired responses; e) modifying, based on said correlating step, said set of parameters associated with said generating step to provide parameters that produce said desired responses; f) generating, responsive to said modified set of parameters, a second set of test stimuli for providing increased test coverage; and g) repeating steps b through f until complete test coverage of said device under test is achieved and all desired responses have been produced.
Claim 8
Dependent Claim
33 words
The method of claim 5 wherein said correlating step includes the steps of analyzing, using Design Of Experiments (DOE) techniques, said parameters and said responses to establish a cause and effect relationship therebetween.
Claim 9
Dependent Claim
13 words
The method according to claim 5 wherein said test stimuli are generated randomly.
Claim 10
Dependent Claim
25 words
The method of claim 5 wherein said modifying step includes creating a model of the system response and performing a minimization/maximization analysis on the model.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |