US5390194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ATG test station
Assignee: Grumman Corp
•
Filing: 1993-11-17
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Granted: 1995-02-14
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Expires: 2013-11-17
Abstract
Abstract A low cost, office environment platform for performing off-station verification and integration of Automatic Test Program Generation test program sets for digital circuit boards includes a general purpose computer which oversees integration of the test program sets developed on the simulator with the digital circuit boards using a basic test control unit such as the HP16500 Logic Analysis System. A method of utilizing this apparatus involves generating and simulating the test program sets and applying the test program sets to the digital circuit boards during development with feedback to the host computer on which the test program sets are generated.
Inventors
- 👤 Thomas M. Mannle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:15
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31912
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
183 words
Apparatus for integrating test program sets for digital circuit boards, the test program sets being output by an automatic test program generation system (ATG), comprising: an ATG host computer which includes means for generating test programs; a general purpose personal computer connected to the ATG host computer for receiving program sets output by the host computer, said general purpose computer including means for running and debugging said ATG test programs provided by the ATG host computer; a basic test unit connected to the general purpose personal computer for generating test patterns in response to running of said test programs by said general purpose computer and applying the test patterns to a digital circuit board under control of the personal computer; and an interface for transferring stimulus data and response data between the basic test unit and the digital circuit board, wherein said ATG host computer includes means for analyzing the performance of ATG test programs run by the general purpose computer which in turn comprises means for analyzing performance of the basic test unit and transmitting results back to the ATG host computer.
Claim 2
Dependent Claim
183 words
Apparatus for integrating test program sets for digital circuit boards, the test program sets being output by an automatic test program generation system (ATG), comprising: an ATG host computer which includes means for generating test programs; a general purpose personal computer connected to the ATG host computer for receiving program sets output by the host computer, said general purpose computer including means for running and debugging said ATG test programs provided by the ATG host computer; a basic test unit connected to the general purpose personal computer for generating test patterns in response to running of said test programs by said general purpose computer and applying the test patterns to a digital circuit board under control of the personal computer; and an interface for transferring stimulus data and response data between the basic test unit and the digital circuit board, wherein said ATG host computer includes means for analyzing the performance of ATG test programs run by the general purpose computer which in turn comprises means for analyzing performance of the basic test unit and transmitting results back to the ATG host computer.
Claim 3
Dependent Claim
18 words
Apparatus as claimed in claim 1, wherein said general purpose computer is an IBM PC or compatible computer.
Claim 4
Dependent Claim
22 words
Apparatus as claimed in claim 1, further comprising a programmable power supply for providing the digital circuit boards with necessary supply voltages.
Claim 5
Dependent Claim
18 words
Apparatus as claimed in claim 1, wherein said computer, test unit, and interface constitute a stand-alone test station.
Claim 6
Dependent Claim
29 words
Apparatus as claimed in claim 1 wherein said personal computer further includes an interface card which provides counter-timer and pulse generator functions for generating control signals for the interface.
Claim 7
Dependent Claim
22 words
Apparatus as claimed in claim 5, wherein said interface card provides a digital multimeter in addition to counter-timer and pulse generator functions.
Claim 8
Dependent Claim
16 words
Apparatus as claimed in claim 1, wherein said test unit is an HP16500 logic analysis system.
Claim 9
Dependent Claim
30 words
Analysis as claimed in claim 5, further comprising stimulus and response channel expander boards for increasing the number of stimulus and response channels provided by the HP16500 Logic Analysis System.
Claim 10
Independent Claim
156 words
A method of developing test programs sets, comprising the steps of a) analyzing a unit under test (UUT), generating a model thereof and programming said model into an automatic test generation system (ATG) host computer; b) using the host computer to generate stimulus test patterns and simulating the patterns in order to determine their effect on the model; c) upon achieving acceptable simulated results, integrating the test patterns into apparatus capable of applying the test patterns to the UUT, by sending the test pattern to a personal Computer and causing .the personal computer to integrate the test patterns into a basic test unit; d) using the basic test unit to apply the test patterns thus generated to the UUT and analyzing the results; e) if the results are acceptable, providing the UUT with sample faults and applying the test pattern; f) if the results are not acceptable, varying the model or stimulus and repeating steps (c)-(e).
Claim 11
Independent Claim
156 words
A method of developing test programs sets, comprising the steps of a) analyzing a unit under test (UUT), generating a model thereof and programming said model into an automatic test generation system (ATG) host computer; b) using the host computer to generate stimulus test patterns and simulating the patterns in order to determine their effect on the model; c) upon achieving acceptable simulated results, integrating the test patterns into apparatus capable of applying the test patterns to the UUT, by sending the test pattern to a personal Computer and causing .the personal computer to integrate the test patterns into a basic test unit; d) using the basic test unit to apply the test patterns thus generated to the UUT and analyzing the results; e) if the results are acceptable, providing the UUT with sample faults and applying the test pattern; f) if the results are not acceptable, varying the model or stimulus and repeating steps (c)-(e).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |