US5297151A
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Adjustable weighted random test pattern generator for logic circuits
Assignee: International Business Machines Corp
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Filing: 1992-06-17
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Granted: 1994-03-22
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Expires: 2012-06-17
Abstract
Abstract A test pattern generator includes a random pattern generator and a shift register. The random pattern generator generates a series of digits which are input to the shift register and stored therein. Each digit output by the random pattern generator has a probability of having a first value, such as representing "1". The output probability of the random pattern generator is adjustable. The shift register has a plurality of outputs for outputting a test pattern comprising the stored digits. The shift register includes a series of latches and at least a first logic circuit connecting the output of the random pattern generator to the input of a first latch, or connecting the output of a latch to the input of a next adjacent latch. In a first state, the logic circuit has an output probability which is independent of the output probability of the random pattern generator. In a second state, the logic circuit has an output probability which is dependent on the output probability of the random pattern generator.
Inventors
- 👤 Matthias Gruetzner
- 👤 Leendert M. Huisman
- 👤 Sandip Kundu
- 👤 Cordt W. Starke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:10
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/3183; G01R31/318385; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
308 words
An apparatus for generating test patterns, said apparatus comprising: a random pattern generator for generating a series of digit signals at an output of the random pattern generator, each digit signal in the series having an initial probability of having a first value, the initial probability being adjustable; a shift register for storing a plurality of digit signals of a test pattern, said shift register having an input for receiving digit signals from the output of the random pattern generator, said shift register having a plurality of outputs for outputting a test pattern comprising the stored digit signals; characterized in that the shift register comprises: a series of latches, each latch having an input and having an output, the input of a first latch being connected to the output of the random pattern generator, the output of each latch being connected to the input of a next adjacent latch, each latch storing one digit signal of a test pattern; and at least a first logic circuit for connecting the output of the random pattern generator to the input of the first latch or for connecting the output of a latch to the input of a next adjacent latch, said logic circuit having first and second states, and a control input for selecting either the first state or the second state, said logic circuit having a data output for outputting a series of digit signals, each digit signal output by the logic circuit having a first output probability of having the first value when the logic circuit is in the first state, the first output probability being independent of the initial probability, each digit signal output by the logic circuit having a second output probability of having the first value when the logic circuit is in the second state, the second output probability being dependent on the initial probability.
Claim 2
Independent Claim
308 words
An apparatus for generating test patterns, said apparatus comprising: a random pattern generator for generating a series of digit signals at an output of the random pattern generator, each digit signal in the series having an initial probability of having a first value, the initial probability being adjustable; a shift register for storing a plurality of digit signals of a test pattern, said shift register having an input for receiving digit signals from the output of the random pattern generator, said shift register having a plurality of outputs for outputting a test pattern comprising the stored digit signals; characterized in that the shift register comprises: a series of latches, each latch having an input and having an output, the input of a first latch being connected to the output of the random pattern generator, the output of each latch being connected to the input of a next adjacent latch, each latch storing one digit signal of a test pattern; and at least a first logic circuit for connecting the output of the random pattern generator to the input of the first latch or for connecting the output of a latch to the input of a next adjacent latch, said logic circuit having first and second states, and a control input for selecting either the first state or the second state, said logic circuit having a data output for outputting a series of digit signals, each digit signal output by the logic circuit having a first output probability of having the first value when the logic circuit is in the first state, the first output probability being independent of the initial probability, each digit signal output by the logic circuit having a second output probability of having the first value when the logic circuit is in the second state, the second output probability being dependent on the initial probability.
Claim 3
Dependent Claim
29 words
An apparatus as claimed in claim 1, characterized in that the latch is a binary electronic latch, and each digit signal has one of only first and second values.
Claim 4
Dependent Claim
57 words
An apparatus as claimed in claim 2, characterized in that the first value of the digit signal represents one, the second value of the digit signal represents zero, and each digit signal generated by the random pattern generator has a probability P 1 of representing one, and has a probability P 0 =1-P 1 of representing zero.
Claim 5
Dependent Claim
83 words
An apparatus as claimed in claim 3, characterized in that each digit signal output by the logic circuit has a probability R 1 of representing one, and has a probability R 0 =1-R 1 of representing zero when the logic circuit is in the first state; and each digit signal output by the logic circuit has a probability Q 1 of representing one, and has a probability Q 0 =1-Q 1 of representing zero when the logic circuit is in the second state.
Claim 6
Dependent Claim
48 words
An apparatus as claimed in claim 4, characterized in that the logic circuit comprises a logical OR gate having a first input connected to the output of the random pattern generator or to the output of a latch, and having a second input connected to a control line.
Claim 7
Dependent Claim
48 words
An apparatus as claimed in claim 4, characterized in that the logic circuit comprises a logical AND gate having a first input connected to the output of the random pattern generator or to the output of a latch, and having a second input connected to a control line.
Claim 8
Dependent Claim
49 words
An apparatus as claimed in claim 4, characterized in that each latch has an input for receiving digit signals from the output of the logic circuit or from the output of a prior adjacent latch, and has an output for outputting digit signals to a circuit to be tested.
Claim 9
Dependent Claim
48 words
An apparatus as claimed in claim 7, further comprising a second logic circuit for connecting the output of a latch to the input of a next adjacent latch, said first logic circuit is arranged in the shift register between the random pattern generator and the second logic circuit.
Claim 10
Independent Claim
174 words
An apparatus for generating test patterns, said apparatus comprising: a random pattern generator for generating a series of digit signals, each digit signal in the series having an initial probability of having a first value, the initial probability being adjustable; at least one latch for storing one digit signal of a test pattern; and a logic circuit having first and second states, a data input for receiving digit signals from the random pattern generator, a control input for selecting either the first or the second state, and a data output for outputting a series of digit signals to the latch, each digit signal output by the logic circuit having a first output probability of having the first value when the logic circuit is in the first state, the first output probability being independent of the initial probability, each digit signal output by the logic circuit having a second output probability of having the first value when the logic circuit is in the second state, the second output probability being dependent on the initial probability.
Claim 11
Independent Claim
174 words
An apparatus for generating test patterns, said apparatus comprising: a random pattern generator for generating a series of digit signals, each digit signal in the series having an initial probability of having a first value, the initial probability being adjustable; at least one latch for storing one digit signal of a test pattern; and a logic circuit having first and second states, a data input for receiving digit signals from the random pattern generator, a control input for selecting either the first or the second state, and a data output for outputting a series of digit signals to the latch, each digit signal output by the logic circuit having a first output probability of having the first value when the logic circuit is in the first state, the first output probability being independent of the initial probability, each digit signal output by the logic circuit having a second output probability of having the first value when the logic circuit is in the second state, the second output probability being dependent on the initial probability.
Claim 12
Dependent Claim
29 words
An apparatus as claimed in claim 9, characterized in that the latch is a binary electronic latch, and each digit signal has one of only first and second values.
Claim 13
Dependent Claim
57 words
An apparatus as claimed in claim 10, characterized in that the first value of the digit signal represents one, the second value of the digit signal represents zero, and each digit signal generated by the random pattern generator has a probability P 1 of representing one, and has a probability P 0 =1-P 1 of representing zero.
Claim 14
Dependent Claim
83 words
An apparatus as claimed in claim 11, characterized in that each digit signal output by the logic circuit has a probability R 1 of representing one, and has a probability R 0 =1-R 1 of representing zero when the logic circuit is in the first state; and each digit signal output by the logic circuit has a probability Q 1 of representing one, and has a probability Q 0 =1-Q 1 of representing zero when the logic circuit is in the second state.
Claim 15
Dependent Claim
48 words
An apparatus as claimed in claim 12, characterized in that the logic circuit comprises a logical OR gate having a first input connected to the output of the random pattern generator or to the output of a latch, and having a second input connected to a control line.
Claim 16
Dependent Claim
48 words
An apparatus as claimed in claim 12, characterized in that the logic circuit comprises a logical AND gate having a first input connected to the output of the random pattern generator or to the output of a latch, and having a second input connected to a control line.
Claim 17
Dependent Claim
40 words
An apparatus as claimed in claim 12, characterized in that the latch has an input for receiving digit signals from the output of the logic circuit, and has an output for outputting digit signals to a circuit to be tested.
Claim 18
Dependent Claim
51 words
An apparatus as claimed in claim 15, further comprising a second latch for storing one digit signal of a test pattern, said second latch having an input for receiving digit signals from the output of the random pattern generator, and having an output for outputting digit signals to the logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-21 | 1997-09-20 | 1998-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-21 | 2001-09-20 | 2002-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-21 | 2005-09-20 | 2006-03-22 | $7700.00 | Window Closed / Lapsed |