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US5680594A
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Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies
Assignee: Apple Inc
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Filing: 1995-05-24
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Granted: 1997-10-21
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Expires: 2015-05-24
Abstract
Abstract A bus interface device for an application specific integrated circuit handles more than two different clock frequencies and allow for real time switching between the clock frequencies by subsystems of the application specific integrated circuit. In a preferred embodiment, a master state machine is provided that includes a plurality of control input lines and a plurality of control output lines, and a plurality of synchronizing state machines each coupled to one of the control output lines of the master state machine and to a separate clock frequency line. The master state machine, based on signals applied to the control input lines, selectively enables the synchronizing state machines to supply the different clock frequencies to the subsystems of the application specific integrated circuit.
Inventors
- 👤 David Charneski
- 👤 Kenneth D. Kieffer
- 👤 John J. Uebelacker
- 👤 Richard A. Wanzenried
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:23
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
160 words
A bus interface device comprising: a master state machine including a plurality of control input lines and a plurality of control output lines; three or more synchronizing state machines, each including a control input line coupled to one of the control output lines of the master state machine and at least one output select line; and clocking means for supplying a different clock frequency signal to each of the synchronizing state machines; wherein said master state machine selectively enables the synchronizing state machines in response to control signals applied to the control input lines of the master state machine; and a plurality of subsystems operable at different clock frequencies, each subsystem including a control input line coupled to the output select line of a corresponding one of the synchronizing state machines, wherein the clocking means supplies the different clock frequency signal to each subsystem that corresponds to the different clock frequency signal supplied to the synchronizing state machine corresponding thereto.
Claim 2
Dependent Claim
160 words
A bus interface device comprising: a master state machine including a plurality of control input lines and a plurality of control output lines; three or more synchronizing state machines, each including a control input line coupled to one of the control output lines of the master state machine and at least one output select line; and clocking means for supplying a different clock frequency signal to each of the synchronizing state machines; wherein said master state machine selectively enables the synchronizing state machines in response to control signals applied to the control input lines of the master state machine; and a plurality of subsystems operable at different clock frequencies, each subsystem including a control input line coupled to the output select line of a corresponding one of the synchronizing state machines, wherein the clocking means supplies the different clock frequency signal to each subsystem that corresponds to the different clock frequency signal supplied to the synchronizing state machine corresponding thereto.
Claim 3
Dependent Claim
27 words
A bus interface device as claimed in claim 1, further comprising clock frequency setting means for changing an operating frequency of at least one of the subsystems.
Claim 4
Dependent Claim
31 words
A bus interface device as claimed in claim 2, wherein the clock frequency setting means comprises a clock multiplexer control circuit including a control input coupled to a subsystem control register.
References Cited (Backward Citations)
US4523274A
Cited
US4819164A
Cited
US4670837A
Cited
US5359727A
Cited
US5197126A
Cited
US5265243A
Cited
US5319772A
Cited
US5535398A
Cited
US5280587A
Cited
US5347559A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |