US5680556A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses
Assignee: Lenovo Singapore Pte Ltd
•
Filing: 1996-09-03
•
Granted: 1997-10-21
•
Expires: 2016-09-03
Abstract
Abstract A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus. Logic is provided to detect during the first ROM CPU cycle whether the ROM is on the peripheral bus or on the local bus, and the MC/PBHB will then either pass the signal to the peripheral bus if that is where the ROM is located, or will not pass it--in which case the local bus controller will take over and read the ROM which must be located on the local bus since it is not located on the peripheral bus.
Inventors
- 👤 Ralph Murray Begun
- 👤 William Robert Greer
- 👤 Christopher Michael Herring
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:21
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403; G06F9/4411
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
366 words
A computer system comprising: a) a processor; b) a processor local bus connected to the processor and having a local bus protocol; c) local bus control circuitry connected to the local bus to generate bus cycles on the local bus conforming to the local bus protocol; d) a peripheral bus having a device select contact and a plurality of address contacts, and a peripheral bus protocol different than the local bus protocol; e) a peripheral bus host bridge disposed between said peripheral bus and the local bus control circuitry to translate said peripheral bus protocol to the local bus protocol, and to translate the local bus protocol to said peripheral bus protocol; f) a clock coupled to the local bus and to said peripheral bus to generate clock cycles on the local bus and said peripheral bus; g) a boot ROM alternatively located on one of the local bus and said peripheral bus, said boot ROM providing the processor with an initial series of boot instructions wherein said boot ROM when located on said peripheral bus includes a protocol interface circuit responsive to an address signal on the address contacts the protocol interface circuit generating a device select status signal on the device select contact in response to a successful address decode status on said peripheral bus; and h) detection logic on said peripheral bus host bridge, responsive to said device select status signal and said clock cycles for detecting said boot ROM located on said peripheral bus, and for detecting, in the alternative, said boot ROM located on the local bus wherein: i) the initial boot instructions are provided to the processor through said peripheral bus host bridge in response to a first predetermined number of said clock cycles and said device select status signal utilizing said peripheral bus protocol on said peripheral bus corresponding to the boot ROM located on said peripheral bus; and in the alternative; and ii) the initial boot instructions are provided to the processor by the local bus control circuitry in response to a second number N of clock cycles, in excess of said first predetermined number of clock cycles corresponding to the boot ROM located on the local bus.
Claim 2
Dependent Claim
366 words
A computer system comprising: a) a processor; b) a processor local bus connected to the processor and having a local bus protocol; c) local bus control circuitry connected to the local bus to generate bus cycles on the local bus conforming to the local bus protocol; d) a peripheral bus having a device select contact and a plurality of address contacts, and a peripheral bus protocol different than the local bus protocol; e) a peripheral bus host bridge disposed between said peripheral bus and the local bus control circuitry to translate said peripheral bus protocol to the local bus protocol, and to translate the local bus protocol to said peripheral bus protocol; f) a clock coupled to the local bus and to said peripheral bus to generate clock cycles on the local bus and said peripheral bus; g) a boot ROM alternatively located on one of the local bus and said peripheral bus, said boot ROM providing the processor with an initial series of boot instructions wherein said boot ROM when located on said peripheral bus includes a protocol interface circuit responsive to an address signal on the address contacts the protocol interface circuit generating a device select status signal on the device select contact in response to a successful address decode status on said peripheral bus; and h) detection logic on said peripheral bus host bridge, responsive to said device select status signal and said clock cycles for detecting said boot ROM located on said peripheral bus, and for detecting, in the alternative, said boot ROM located on the local bus wherein: i) the initial boot instructions are provided to the processor through said peripheral bus host bridge in response to a first predetermined number of said clock cycles and said device select status signal utilizing said peripheral bus protocol on said peripheral bus corresponding to the boot ROM located on said peripheral bus; and in the alternative; and ii) the initial boot instructions are provided to the processor by the local bus control circuitry in response to a second number N of clock cycles, in excess of said first predetermined number of clock cycles corresponding to the boot ROM located on the local bus.
Claim 3
Dependent Claim
287 words
In a personal computer system having a CPU and configured to generate clock cycles over a local bus and a peripheral bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to be accessed to provide the CPU initialization instructions from the peripheral bus or to be accessed to provide the CPU initialization instructions from the local bus as a function of a presence of the ROM chip on the peripheral bus or a presence of the ROM chip on the local bus, respectively, a method of accessing the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the peripheral bus or whether the ROM chip is present on the local bus, comprising the steps of: generating a device select status signal on the peripheral bus in response to a successful address decode status on the peripheral bus as a function of a presence of the ROM chip on the peripheral bus; generating a first predetermined number of clock cycles in the personal computer system; generating a second predetermined number of clock cycles, in the personal computer system prior to generating any said device select status signal in response to a presence of the ROM chip on the local bus; detecting the ROM chip being present on the peripheral bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of the second predetermined number of clock cycles prior to any generation of said device select status signal; and accessing the ROM chip and the initialization instructions.
Claim 4
Dependent Claim
287 words
In a personal computer system having a CPU and configured to generate clock cycles over a local bus and a peripheral bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to be accessed to provide the CPU initialization instructions from the peripheral bus or to be accessed to provide the CPU initialization instructions from the local bus as a function of a presence of the ROM chip on the peripheral bus or a presence of the ROM chip on the local bus, respectively, a method of accessing the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the peripheral bus or whether the ROM chip is present on the local bus, comprising the steps of: generating a device select status signal on the peripheral bus in response to a successful address decode status on the peripheral bus as a function of a presence of the ROM chip on the peripheral bus; generating a first predetermined number of clock cycles in the personal computer system; generating a second predetermined number of clock cycles, in the personal computer system prior to generating any said device select status signal in response to a presence of the ROM chip on the local bus; detecting the ROM chip being present on the peripheral bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of the second predetermined number of clock cycles prior to any generation of said device select status signal; and accessing the ROM chip and the initialization instructions.
Claim 5
Dependent Claim
38 words
The method of accessing the ROM chip including the CPU initialization instructions as defined in claim 2; further including the step of: commencing initialization of the personal computer system in accordance with the initialization instructions from the CPU.
Claim 6
Dependent Claim
307 words
In a personal computer system having a CPU and configured to generate cloak cycles over a local bus having a first protocol, and an another bus having a protocol different than the first protocol and a host bridge circuit coupling the local bus and another bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to be accessed to provide the CPU initialization instructions from the another bus or to be accessed to provide the CPU initialization instructions from the local bus as a function of a presence of the ROM chip on the another bus or a presence of the ROM chip on the local bus, respectively, a method of accessing the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the another bus having the protocol different than the first protocol or whether the ROM chip is present on the local bus having the first protocol, comprising the steps of: generating a device select status signal on the another bus having the protocol different than the first protocol in response to receipt of an address decode status from the another bus by the host bridge circuit as a function of a presence of the ROM chip on the another bus; generating a first predetermined number of clock cycles in the personal computer system; detecting the ROM chip being present on the another bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of a second number of clock cycles of the predetermined number of clock cycles prior to generating any said device select status signal; and accessing the ROM chip and the initialization instructions.
Claim 7
Dependent Claim
307 words
In a personal computer system having a CPU and configured to generate cloak cycles over a local bus having a first protocol, and an another bus having a protocol different than the first protocol and a host bridge circuit coupling the local bus and another bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to be accessed to provide the CPU initialization instructions from the another bus or to be accessed to provide the CPU initialization instructions from the local bus as a function of a presence of the ROM chip on the another bus or a presence of the ROM chip on the local bus, respectively, a method of accessing the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the another bus having the protocol different than the first protocol or whether the ROM chip is present on the local bus having the first protocol, comprising the steps of: generating a device select status signal on the another bus having the protocol different than the first protocol in response to receipt of an address decode status from the another bus by the host bridge circuit as a function of a presence of the ROM chip on the another bus; generating a first predetermined number of clock cycles in the personal computer system; detecting the ROM chip being present on the another bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of a second number of clock cycles of the predetermined number of clock cycles prior to generating any said device select status signal; and accessing the ROM chip and the initialization instructions.
Claim 8
Dependent Claim
264 words
A data processing system having multiple buses for accessing a boot ROM, having initialization instructions, disposed on one bus of the multiple buses, comprising: a local bus having a first protocol; a CPU connected to the local bus; an another bus having a protocol different than the first protocol; a clock coupled to the local bus and to the another bus for generating clock cycles on the local bus and the another bus; a bus host bridge connecting the local bus having the first protocol to the another bus having the protocol different than the first protocol, for translating the first protocol to the protocol different than the first protocol and for translating the protocol different than the first protocol to the first protocol, sending an address signal to the another bus to determine a presence status of the boot ROM on the another bus; a protocol interface circuit on the another bus generating a device select status signal in response to a presence of the boot ROM on the another bus; and determination logic on the bus host bridge either responsive to the device select status signal being generated within a predetermined number of clock cycles for accessing the boot ROM on the another bus and for reading the initialization Instructions on the boot ROM, or for accessing the boot ROM on the local bus in response to a number N of clock cycles in excess of the predetermined number of clock cycles, being generated before the generation of the device select status signal for reading the initialization instructions on the boot ROM.
Claim 9
Dependent Claim
264 words
A data processing system having multiple buses for accessing a boot ROM, having initialization instructions, disposed on one bus of the multiple buses, comprising: a local bus having a first protocol; a CPU connected to the local bus; an another bus having a protocol different than the first protocol; a clock coupled to the local bus and to the another bus for generating clock cycles on the local bus and the another bus; a bus host bridge connecting the local bus having the first protocol to the another bus having the protocol different than the first protocol, for translating the first protocol to the protocol different than the first protocol and for translating the protocol different than the first protocol to the first protocol, sending an address signal to the another bus to determine a presence status of the boot ROM on the another bus; a protocol interface circuit on the another bus generating a device select status signal in response to a presence of the boot ROM on the another bus; and determination logic on the bus host bridge either responsive to the device select status signal being generated within a predetermined number of clock cycles for accessing the boot ROM on the another bus and for reading the initialization Instructions on the boot ROM, or for accessing the boot ROM on the local bus in response to a number N of clock cycles in excess of the predetermined number of clock cycles, being generated before the generation of the device select status signal for reading the initialization instructions on the boot ROM.
Claim 10
Dependent Claim
281 words
In a personal computer system having a CPU and configured to generate clock cycles over a local bus and a peripheral bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to detect the ROM chip containing the CPU initialization instructions on the peripheral bus or to detect the ROM chip containing the CPU initialization instructions on the local bus as a function of a presence of the ROM chip on the peripheral bus or a presence of the ROM chip on the local bus, respectively, a method of detecting the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the peripheral bus or whether the ROM chip is present on the local bus, comprising the steps of: generating a device select status signal on the peripheral bus in response to a successful address decode status on the peripheral bus as a function of a presence of the ROM chip on the peripheral bus; generating a first predetermined number of clock cycles in the personal computer system; generating a second predetermined number of clock cycles in the personal computer system prior to any generation of said device select status signal in response to a presence of the ROM chip on the local bus; and detecting the ROM chip being present on the peripheral bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of the second predetermined number of clock cycles prior to generating any said device select status signal.
Claim 11
Dependent Claim
281 words
In a personal computer system having a CPU and configured to generate clock cycles over a local bus and a peripheral bus in the personal computer system, including a ROM chip containing CPU initialization instructions and configured to detect the ROM chip containing the CPU initialization instructions on the peripheral bus or to detect the ROM chip containing the CPU initialization instructions on the local bus as a function of a presence of the ROM chip on the peripheral bus or a presence of the ROM chip on the local bus, respectively, a method of detecting the ROM chip including the CPU initialization instructions regardless of whether the ROM chip is present on the peripheral bus or whether the ROM chip is present on the local bus, comprising the steps of: generating a device select status signal on the peripheral bus in response to a successful address decode status on the peripheral bus as a function of a presence of the ROM chip on the peripheral bus; generating a first predetermined number of clock cycles in the personal computer system; generating a second predetermined number of clock cycles in the personal computer system prior to any generation of said device select status signal in response to a presence of the ROM chip on the local bus; and detecting the ROM chip being present on the peripheral bus as a function of the combination of the device select status signal and the first predetermined number of clock cycles, or detecting the ROM chip being present on the local bus as a function of the generation of the second predetermined number of clock cycles prior to generating any said device select status signal.
References Cited (Backward Citations)
JPS5437646A
Cited
US4626986A
Cited
US4727491A
Cited
JPS6273354A
Cited
JPS62226356A
Cited
JPS63244231A
Cited
JPS63271528A
Cited
US5148389A
Cited
US5123092A
Cited
US5321827A
Cited
US5355489A
Cited
JPH0460840A
Cited
JPH0488424A
Cited
US5274816A
Cited
US5410707A
Cited
US5471674A
Cited
US5522050A
Cited
US5515514A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |