US5515514A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral processor card for upgrading a computer
Assignee: Apple Inc
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Filing: 1995-09-28
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Granted: 1996-05-07
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Expires: 2015-09-28
Abstract
Abstract Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.
Inventors
- 👤 Michael J. Dhuey
- 👤 Farid A. Yazdy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0866; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
166 words
A peripheral processor card for upgrading a host personal computer, said host personal computer including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a first processor, system memory, and input-output (I/O) units, said peripheral processor card comprising: a second processor; a peripheral address bus coupled between said second processor and said host address bus; a peripheral data bus coupled between said second processor and said host data bus; and a bus translator unit coupled to said peripheral address bus and to said peripheral data bus and having a plurality of programmable control registers to generate a plurality of control signals to said first processor and to said second processor, said bus translator unit further generating processor shutdown signals which, when received by said first processor, place said first processor in a shutdown state, said second processor thereafter having control of said system memory and I/O units within said host personal computer.
Claim 2
Dependent Claim
166 words
A peripheral processor card for upgrading a host personal computer, said host personal computer including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a first processor, system memory, and input-output (I/O) units, said peripheral processor card comprising: a second processor; a peripheral address bus coupled between said second processor and said host address bus; a peripheral data bus coupled between said second processor and said host data bus; and a bus translator unit coupled to said peripheral address bus and to said peripheral data bus and having a plurality of programmable control registers to generate a plurality of control signals to said first processor and to said second processor, said bus translator unit further generating processor shutdown signals which, when received by said first processor, place said first processor in a shutdown state, said second processor thereafter having control of said system memory and I/O units within said host personal computer.
Claim 3
Dependent Claim
15 words
A peripheral processor card as in claim 1 and further comprising: a cache memory system.
Claim 4
Dependent Claim
30 words
A peripheral processor card as in claim 2 wherein said cache memory system comprises: a cache data memory coupled to said peripheral address bus and to said peripheral data bus.
Claim 5
Dependent Claim
31 words
A peripheral processor card as in claim 3 wherein said cache memory system further comprises: a cache tag memory coupled to said peripheral address bus and to said bus translator unit.
Claim 6
Dependent Claim
211 words
A peripheral processor card as in claim 4 wherein said second processor successively generates current address signals on said peripheral address bus, and said bus translator unit generates active and inactive address latch control signals, and further comprising: an address bus coupling, which couples said peripheral address bus to said cache data memory, including an address latch having a latch input terminal connected to said peripheral address bus, and a latch output terminal, and being responsive to active address latch control signals to latch and hold the current address signal at the latch output terminal while the current burst read operation is in progress, until receiving a subsequent active address latch control signal, and a latched-address bus connected from said latch output terminal to said data cache; wherein, after generating an active address latch control signal, and without waiting for current burst read operation completion, said bus translator unit generates an acknowledge signal which causes said second processor to supplant the current address signal by generating a next address signal on said peripheral address bus; and, upon completion of the current burst read operation, said bus translator unit generates a subsequent active address latch control signal which causes said address latch to latch said next address signal for the current address.
Claim 7
Dependent Claim
20 words
A cache memory system as in claim 5 wherein said latched-address bus is connected also to said host address bus.
Claim 8
Dependent Claim
32 words
A peripheral processor card as in claim 1 and further comprising system read only memory means, coupled to said peripheral address bus and to said peripheral data bus, for providing program signals.
Claim 9
Dependent Claim
15 words
A peripheral processor card as in claim 7 and further comprising: a cache memory system.
Claim 10
Dependent Claim
30 words
A peripheral processor card as in claim 8 wherein said cache memory system comprises: a cache data memory coupled to said peripheral address bus and to said peripheral data bus.
Claim 11
Dependent Claim
31 words
A peripheral processor card as in claim 9 wherein said cache memory system further comprises: a cache tag memory coupled to said peripheral address bus and to said bus translator unit.
Claim 12
Dependent Claim
67 words
The peripheral processor card as set forth in claim 1, wherein said bus translator unit comprises first and second processor control blocks receiving a plurality of input clock and control signals, said first processor control block transmitting a corresponding plurality of first processsor control signals to said first processor, said second processor control block transmitting a corresponding plurality of second processor control signals to said second processor.
Claim 13
Dependent Claim
58 words
The processor card of claim 1, wherein the first processor has a JTAG test port, the bus translator unit (BTU) is coupled to the JTAG test port, and the shutdown signals generated by the BTU include RESET, TCK, and TMS signals which, when received by the first processor, place the first processor in a nonfunctional, high impedance state.
Claim 14
Dependent Claim
31 words
The processor card of claim 1, wherein the bus translator unit translates Power PC 601 64-bit wide data bus transactions into M68000 family 32-bit wide data bus transactions, and vice versa.
Claim 15
Independent Claim
169 words
A method for upgrading a host personal computer, said host personal computer including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a first processor, system memory, and input-output (I/O) units, said method comprising the steps of: providing a second processor; providing a peripheral address bus coupled between said second processor and said host address bus; providing a peripheral data bus coupled between said second processor and said host data bus; providing a bus translator unit coupled to said peripheral address bus and to said peripheral data bus and having a plurality of programmable control registers to generate a plurality of control signals to said first processor and to said second processor, said bus translator unit further generating processor shutdown signals which, when received by said first processor, place said first processor in a shutdown state; and thereafter granting said second processor control of said system memory and I/O units within said host personal computer.
Claim 16
Independent Claim
169 words
A method for upgrading a host personal computer, said host personal computer including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a first processor, system memory, and input-output (I/O) units, said method comprising the steps of: providing a second processor; providing a peripheral address bus coupled between said second processor and said host address bus; providing a peripheral data bus coupled between said second processor and said host data bus; providing a bus translator unit coupled to said peripheral address bus and to said peripheral data bus and having a plurality of programmable control registers to generate a plurality of control signals to said first processor and to said second processor, said bus translator unit further generating processor shutdown signals which, when received by said first processor, place said first processor in a shutdown state; and thereafter granting said second processor control of said system memory and I/O units within said host personal computer.
Claim 17
Dependent Claim
17 words
A method as in claim 14 and further comprising the step of providing a cache memory system.
Claim 18
Dependent Claim
33 words
A method as in claim 15 wherein said step of providing a cache memory system comprises providing a cache data memory coupled to said peripheral address bus and to said peripheral data bus.
Claim 19
Dependent Claim
34 words
A method as in claim 16 wherein said step of providing a cache memory system further comprises providing a cache tag memory coupled to said peripheral address bus and to said bus translator unit.
Claim 20
Dependent Claim
240 words
A method as in claim 17 wherein said step of providing a second processor includes using said second processor successively to generate current address signals on said peripheral address bus; said step of providing a bus translator unit includes using said bus translator unit to generate active and inactive address latch control signals; and said step of providing a peripheral address bus further comprises providing an address bus coupling, to couple said peripheral address bus to said cache data memory, including an address latch having a latch input terminal connected to said peripheral address bus, and a latch output terminal, and being responsive to active address latch control signals to latch and hold the current address signal at the latch output terminal while the current burst read operation is in progress, until receiving a subsequent active address latch control signal, and a latched-address bus connected from said latch output terminal to said data cache; and, after generating an active address latch control signal, and without waiting for current burst read operation completion, generating, with said bus translator unit, an acknowledge signal which causes said second processor to supplant the current address signal by producing a next address signal on said peripheral address bus; and, upon completion of the current burst read operation, generating, with said bus translator unit, a subsequent active address latch control signal which causes said address latch to latch said next address signal for the current address.
Claim 21
Dependent Claim
26 words
A method as in claim 18 wherein said step of providing an address bus coupling comprises connecting said latched-address bus also to said host address bus.
Claim 22
Dependent Claim
34 words
A method as in claim 14 and comprising the further step of coupling a system read only memory means to said peripheral address bus and to said peripheral data bus, for providing program signals.
Claim 23
Dependent Claim
60 words
The method of claim 14, wherein the step of providing a bus translator unit (BTU) includes coupling said BTU to a JTAG test port of the first processor, and the step of generating processor shutdown signals includes generating RESET, TCK, and TMS signals which, when received by the first processor, place the first processor in a nonfunctional, high impedance state.
Claim 24
Dependent Claim
41 words
The method of claim 14, wherein the step of providing a bus translator unit is followed by using said BTU for translating Power PC 601 64-bit wide data bus transactions into M68000 family 32-bit wide data bus transactions, and vice versa.
Claim 25
Dependent Claim
248 words
A peripheral processor card for upgrading a host computer system, said host computer system including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a host processor operable according to a first signal convention, host memory, and input-output units; said peripheral processor card comprising: a peripheral processor operable according to a second signal convention incompatible with said first convention, which successively generates current address signals; a peripheral address bus coupled between said peripheral processor and said host address bus; a peripheral data bus coupled between said peripheral processor and said host data bus; a bus translator unit coupled to said peripheral address bus and to said peripheral data bus, and generating control signals including, in response to a power-up condition, a shutdown "JTAG" signal which shuts down said host processor, and active and inactive address latch control signals and other signals which interface usages of said peripheral address bus and said peripheral data bus between, on one side, said peripheral processor and, on another side, said host address bus and said host data bus; a system read only memory, coupled to said peripheral address bus and to said peripheral data bus, for providing program data; and a cache memory system including a cache tag memory coupled to said peripheral address bus and to said bus translator unit, and a cache data memory coupled to said peripheral address bus and to said peripheral data bus.
Claim 26
Dependent Claim
248 words
A peripheral processor card for upgrading a host computer system, said host computer system including a host address bus and a host data bus, and, operatively connected to said host address bus and to said host data bus, a host processor operable according to a first signal convention, host memory, and input-output units; said peripheral processor card comprising: a peripheral processor operable according to a second signal convention incompatible with said first convention, which successively generates current address signals; a peripheral address bus coupled between said peripheral processor and said host address bus; a peripheral data bus coupled between said peripheral processor and said host data bus; a bus translator unit coupled to said peripheral address bus and to said peripheral data bus, and generating control signals including, in response to a power-up condition, a shutdown "JTAG" signal which shuts down said host processor, and active and inactive address latch control signals and other signals which interface usages of said peripheral address bus and said peripheral data bus between, on one side, said peripheral processor and, on another side, said host address bus and said host data bus; a system read only memory, coupled to said peripheral address bus and to said peripheral data bus, for providing program data; and a cache memory system including a cache tag memory coupled to said peripheral address bus and to said bus translator unit, and a cache data memory coupled to said peripheral address bus and to said peripheral data bus.
Claim 27
Dependent Claim
184 words
A peripheral processor card as in claim 23 and further comprising: an address bus coupling, which couples said peripheral address bus to said cache data memory, including an address latch having a latch input terminal connected to said peripheral address bus, and a latch output terminal, and being responsive to active address latch control signals to latch and hold the current address signal at the latch output terminal while the current burst read operation is in progress, until receiving a subsequent active address latch control signal, and a latched-address bus connected from said latch output terminal to said data cache; wherein, after generating an active address latch control signal, and without waiting for current burst read operation completion, said bus translator unit generates an acknowledge signal which causes said second processor to supplant the current address signal by generating a next address signal on said peripheral address bus; and, upon completion of the current burst read operation, said bus translator unit generates a subsequent active address latch control signal which causes said address latch to latch said next address signal for the current address.
Claim 28
Dependent Claim
58 words
The processor card of claim 23, wherein the first processor has a JTAG test port, the bus translator unit (BTU) is coupled to the JTAG test port, and the shutdown signals generated by the BTU include RESET, TCK, and TMS signals which, when received by the first processor, place the first processor in a nonfunctional, high impedance state.
Claim 29
Dependent Claim
31 words
The processor card of claim 23, wherein the bus translator unit translates Power PC 601 64-bit wide data bus transactions into M68000 family 32-bit wide data bus transactions, and vice versa.
References Cited (Backward Citations)
US4794523A
Cited
US5297272A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |