Patent US5680362A successfully refreshed from Google Patents.
US5680362A
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Circuit and method for accessing memory cells of a memory device
Assignee: United Microelectronics Corp
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Filing: 1996-05-30
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Granted: 1997-10-21
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Expires: 2016-05-30
Abstract
Abstract A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.
Inventors
- 👤 Michael C. Parris
- 👤 Douglas B. Butler
- 👤 Kim C. Hardee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G06; G06F; G06F12/00; G11C29/18; G11C29/30; G11C29/34; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
175 words
In a memory device having rows and columns of memory cells together forming a memory cell array and addressing circuitry operative responsive to address select signals for addressing selected rows of the memory cell array, a combination with the addressing circuitry of a row predecoder for receiving signals representative of the address select signals and a test mode signal and for generating row select signals for permitting addressing of selected rows of the memory cell array, said predecoder comprising: decoding circuitry coupled to receive the signals representative of the address select signals, said decoding circuitry for generating the row select signals permitting the addressing of the selected rows responsive to values of the signals representative of the address select signals; and test mode circuitry coupled to receive the test mode signal and coupled to said decoding circuitry, said test mode circuitry operative responsive to reception of the test mode signal for causing the decoding circuitry to generate the row select signals for permitting concurrent addressing of at least two rows of the memory cell array.
Claim 2
Dependent Claim
175 words
In a memory device having rows and columns of memory cells together forming a memory cell array and addressing circuitry operative responsive to address select signals for addressing selected rows of the memory cell array, a combination with the addressing circuitry of a row predecoder for receiving signals representative of the address select signals and a test mode signal and for generating row select signals for permitting addressing of selected rows of the memory cell array, said predecoder comprising: decoding circuitry coupled to receive the signals representative of the address select signals, said decoding circuitry for generating the row select signals permitting the addressing of the selected rows responsive to values of the signals representative of the address select signals; and test mode circuitry coupled to receive the test mode signal and coupled to said decoding circuitry, said test mode circuitry operative responsive to reception of the test mode signal for causing the decoding circuitry to generate the row select signals for permitting concurrent addressing of at least two rows of the memory cell array.
Claim 3
Dependent Claim
57 words
The predecoder of claim 1 wherein the memory device comprises a dynamic random access memory and wherein, in the absence of reception of the test mode signal by the test mode circuitry generation of the row select signals by said decoding circuitry permits addressing of one selected row of memory cells of the array of memory cells.
Claim 4
Dependent Claim
38 words
The predecoder of claim 2 wherein the address select signals comprise parallel binary signals and wherein said decoding circuitry generates the row select signal when the parallel binary signals are of a first logical combination of signal values.
Claim 5
Dependent Claim
50 words
The predecoder of claim 3 wherein said test mode circuitry, upon reception of the test mode signal, causes said decoding circuitry to generate the row address select signal when the parallel binary signals are of the first logical combination of signal values and a second logical combination of signal values.
Claim 6
Dependent Claim
35 words
The predecoder of claim 4 wherein the first logical combination and the second logical combination of signal values, respectively, differ from one another by a value of one binary signal of the parallel binary signals.
Claim 7
Dependent Claim
63 words
The predecoder of claim 3 where said test mode circuitry, upon reception of the test mode signal, causes said decoding circuitry to generate the row address signals when the parallel binary signals are of the first logical combination of signal values, a second logical combination of signal values, a third logical combination of signal values, and a fourth logical combination of signal values.
Claim 8
Dependent Claim
39 words
The predecoder of claim 3 wherein said decoding circuitry comprises a plurality of decoders, each decoder of said plurality of decoders coupled to receive said address select signals and each decoder for generating at least one row select signal.
Claim 9
Dependent Claim
36 words
The predecoder of claim 7 wherein the decoders of said plurality of decoders correspond in number with a number of logical combinations of signal values permitted of the parallel binary signals forming the address select signals.
Claim 10
Dependent Claim
78 words
The predecoder of claim 3 wherein the parallel binary signals forming the address select signals comprise at least a three-bit signal generated on at least a first line, a second line, and a third line, and wherein said decoding circuitry includes at least a first input pad, a second input pad, and a third input pad coupled to receive said first line, said second line, and said third line, respectively, upon which the address select signals are generated.
Claim 11
Dependent Claim
33 words
The predecoder of claim 9 wherein said decoding circuitry forms a shunt circuit to shunt the third input pad to a selected signal value when the test mode select signal is received thereat.
Claim 12
Dependent Claim
17 words
The predecoder of claim 1 further comprising a test mode generator for generating the test mode signal.
Claim 13
Dependent Claim
27 words
The predecoder of claim 11 wherein said test mode generator generates the test mode signal to stress groups of rows of memory cells of the memory device.
Claim 14
Dependent Claim
62 words
The predecoder of claim 1 wherein the memory device comprises a dynamic random access memory and wherein the test mode signal is generated responsive to times in which a row address select signal, a column address select signal, and a write enable signal is generated in a selected sequence and selected ones of the address select signals are of selected signal values.
Claim 15
Independent Claim
175 words
A method for generating a row select signal to select addressing of selected rows of memory cells of a memory cell array of a memory device, said method comprising the steps of: applying address select signals to the memory device; when testing the memory cell array, further applying a test mode select signal to the memory device; generating a first row select signal on a first selected word line, the first row select signal for selecting addressing of a first selected row of memory cells when the address select signals applied to the memory device during said first step of applying are of a first selected value; further generating at least a second row select signal on at least a second selected word line, the second selected row select signal for selecting concurrent addressing of at least a second selected row of memory cells when the address select signals are of at least a second selected value and the test mode select signal is applied to the memory device during said step of further applying.
Claim 16
Independent Claim
175 words
A method for generating a row select signal to select addressing of selected rows of memory cells of a memory cell array of a memory device, said method comprising the steps of: applying address select signals to the memory device; when testing the memory cell array, further applying a test mode select signal to the memory device; generating a first row select signal on a first selected word line, the first row select signal for selecting addressing of a first selected row of memory cells when the address select signals applied to the memory device during said first step of applying are of a first selected value; further generating at least a second row select signal on at least a second selected word line, the second selected row select signal for selecting concurrent addressing of at least a second selected row of memory cells when the address select signals are of at least a second selected value and the test mode select signal is applied to the memory device during said step of further applying.
Claim 17
Dependent Claim
79 words
The method of claim 14 wherein the address select signals applied to the decoding circuitry during said step of applying comprise at least three-bit binary signals applied to the memory device on at least a first line, a second line, and a third line and wherein said step of generating comprises generating the first row select signal when the binary signals applied on the first line, the second line, and the third line are each of first selected values.
Claim 18
Dependent Claim
40 words
The method of claim 15 wherein said step of further generating comprises generating at least the second row select signal when the binary signals applied on the first line and the second line are each of the first selected value.
Claim 19
Dependent Claim
31 words
The method of claim 15 wherein the memory device comprises decoding circuitry and wherein the address select signals generated during said first step of applying are applied to the decoding circuitry.
Claim 20
Dependent Claim
31 words
The method of claim 14 wherein said step of generating comprises biasing the first selected word line and, thereafter, said step of further generating comprises biasing the second selected word line.
Claim 21
Dependent Claim
144 words
A circuit for increasing rates at which memory cells of a memory device are stressed during testing thereof, the memory cells positioned in rows and columns to form an array of memory cells and the memory device coupled to receive address select signals, said circuit comprising: a test mode signal generator for generating a test mode signal; and a memory cell array decoding device coupled to receive the test mode signal generated by said test mode signal generator and the address select signals, said memory cell array decoding device for generating row select signals of values determinative of which of the rows of memory cells of the array are to be stressed, the row select signals of values causing selection of an increased number of rows of the memory cells of the array to be concurrently stressed when the test mode signal is generated.
Claim 22
Dependent Claim
144 words
A circuit for increasing rates at which memory cells of a memory device are stressed during testing thereof, the memory cells positioned in rows and columns to form an array of memory cells and the memory device coupled to receive address select signals, said circuit comprising: a test mode signal generator for generating a test mode signal; and a memory cell array decoding device coupled to receive the test mode signal generated by said test mode signal generator and the address select signals, said memory cell array decoding device for generating row select signals of values determinative of which of the rows of memory cells of the array are to be stressed, the row select signals of values causing selection of an increased number of rows of the memory cells of the array to be concurrently stressed when the test mode signal is generated.
Claim 23
Dependent Claim
25 words
The circuit of claim 19 further comprising a word line drive device, said word line drive device for altering values of the row select signals.
Claim 24
Dependent Claim
167 words
A circuit for increasing rates at which memory cells of a memory device are stressed during testing thereof, the memory cells positioned in rows and columns to form an array of memory cells, the rows of the memory cells addressed byway of word select lines, and the memory device coupled to receive address select signals, said circuit comprising: a test mode signal generator for generating a test mode signal; a word line drive device coupled to receive the test mode signal generated by said test mode signal generator, said word line drive device for causing generation of a row select signal on at least one additional word select line, thereby to concurrently address at least one additional row of memory cells when the test mode signal is generated; a memory cell array decoding device coupled to receive the address select signals, said memory cell array decoding device for generating a row select signal on a selected word select line to address a selected row of memory cells.
Claim 25
Dependent Claim
167 words
A circuit for increasing rates at which memory cells of a memory device are stressed during testing thereof, the memory cells positioned in rows and columns to form an array of memory cells, the rows of the memory cells addressed byway of word select lines, and the memory device coupled to receive address select signals, said circuit comprising: a test mode signal generator for generating a test mode signal; a word line drive device coupled to receive the test mode signal generated by said test mode signal generator, said word line drive device for causing generation of a row select signal on at least one additional word select line, thereby to concurrently address at least one additional row of memory cells when the test mode signal is generated; a memory cell array decoding device coupled to receive the address select signals, said memory cell array decoding device for generating a row select signal on a selected word select line to address a selected row of memory cells.
Claim 26
Dependent Claim
176 words
A circuit for generating a row select signal to select addressing of selected rows of memory cells of a memory cell array of a memory device, said circuit comprising: means for applying address select signals to the memory device; means for applying a test mode select signal to the memory device when testing the memory cell; means for generating a first row select signal on a first selected word line, the first row select signal for selecting addressing of a first selected row of memory cells when the address select signals applied to the memory device by said means for applying are of a first selected value; means for further generating at least a second row select signal on at least a second selected word line, the second selected row select signal for concurrently selecting addressing of at least a second selected row of memory cells when the address select signals are of at least a second selected value and the test mode select signal is applied to the memory device by said means for applying.
Claim 27
Dependent Claim
176 words
A circuit for generating a row select signal to select addressing of selected rows of memory cells of a memory cell array of a memory device, said circuit comprising: means for applying address select signals to the memory device; means for applying a test mode select signal to the memory device when testing the memory cell; means for generating a first row select signal on a first selected word line, the first row select signal for selecting addressing of a first selected row of memory cells when the address select signals applied to the memory device by said means for applying are of a first selected value; means for further generating at least a second row select signal on at least a second selected word line, the second selected row select signal for concurrently selecting addressing of at least a second selected row of memory cells when the address select signals are of at least a second selected value and the test mode select signal is applied to the memory device by said means for applying.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |