Semiconductor memory device with a test mode

Abstract

Abstract A semiconductor memory device characterized by the fact that the dynamic test time of the semiconductor memory device can be shortened, and the power consumption can be cut. In the dynamic test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time. <IMAGE>

Inventors

• 👤 Kiyotaka C/O Texas Inst. Japan Ltd. Okuzawa
• 👤 Yoshihiro C/O Texas Inst. Japan Ltd. Ogata
• 👤 Takashi Inui

Bibliographic Details