EP0609577A2
Expired / Lapsed
EP
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Dram variable row select
Assignee: UMC Japan Co Ltd
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Filing: 1993-11-09
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Granted: —
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Expires: 2013-11-09
Abstract
Abstract A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration (44a, 46a) that blocks certain address bits, then substitutes active bits in their place to the address decoder (20). The circuit also includes a controller (50) that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder (20) for full user control.
Inventors
- 👤 Michael C. Parris
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 17:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/406; G11C2211/00; G11C2211/401; G11C2211/406; G11C2211/4065
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
76 words
A variable row select circuit for an integrated circuit characterized by a variable bit select circuit (40) having inputs coupled to receive a plurality of address bits (A0-A2) and a control signal (LP/FR, LOWPWR, FASTRFR\), and having an output (22a-22f), at least one of the address bits (A0-A2) being blocked or passed depending on said control signal (LP/FR, LOWPWR, FASTRFR\), and an address decoder (20) coupled to receive the output to enable access to memory data.
Claim 2
Dependent Claim
34 words
The circuit of Claim 1 further characterized by an address latch (12) coupled to receive and latch said address bits (A0-A2), and provide the address bits (A0-A2) to said variable bit select circuit (40).
Claim 3
Dependent Claim
53 words
The circuit of any preceding claim further characterized by an output enable circuit (16) coupled to receive the output of said variable bit select circuit (40) and an enable signal (ABE), wherein in said output enable circuit (16) passes the output to said address decoder (20) in response to the enable signal (ABE).
Claim 4
Dependent Claim
32 words
The circuit of any preceding claim wherein the integrated circuit is a memory device and further comprising a plurality of address buffers (11a-11c) coupled to receive a plurality of address bits (A0-A2).
Claim 5
Dependent Claim
72 words
The circuit of any preceding claim wherein said variable bit select circuit (40) includes at least one block/pass element (44a, 44b, 46a, 46b) coupled to receive the at least one address bit (A0-A2) and the control signal (LP/FR, LOWPWR, FASTRFR\), wherein the at least one block/pass element (44a, 44b, 46a, 46b) blocks or passes the at least one of the address bits (A0-A2) in response to the control signal (LP/FR, LOWPWR, FASTRFR\).
Claim 6
Dependent Claim
26 words
The circuit of any preceding claim wherein said variable bit select circuit (40) substitutes an active signal for the at least one blocked address bit (A0-A2).
Claim 7
Dependent Claim
159 words
The circuit of Claims 5 and 6 wherein the at least one block/pass element (44a, 44b, 46a, 46b) includes a selection transistor (44a) and a pull-up transistor (46a) each having a respective control electrode and a respective source-drain path, the control electrodes of the select and pull-up transistors (44a, 46a) being coupled to said control signal (LP/FR, LOWPWR, FASTRFR\), the source-drain path of the selection transistor (44a) being coupled to receive the at least one of the address bits (A0-A2) and coupled to an output line (22a), said at least one of the address bits (A0-A2) selectively supplied to the output line (22a) responsive to a first state of the control signal (LP/FR, LOWPWR, FASTRFR\), the source-drain path of the pull-up transistor (46a) being coupled to a power supply and to the output line (22a) and selectively coupling the power supply to the output line (22a) in response to a second state of the control signal (LP/FR, LOWPWR, FASTRFR\).
Claim 8
Dependent Claim
62 words
The circuit of any preceding claim further characterized by a variable bit select controller (50) coupled to receive at least one signal (RE) and coupled to the variable bit select circuit (40), said variable bit select controller (50) providing at least one enable signal (LP/FR, LOWPWR, FASTRFR\) to said variable bit select circuit (40) responsive to the at least one signal (RE).
Claim 9
Independent Claim
56 words
A method of controlling the output of an address circuit characterized by the steps of passing all address bits (A0-A2) if control signal (LP/FR, LOWPWR, FASTRFR\) has a first state, blocking at least one of the address bits if the control signal has a second state, and substituting a signal for a blocked address bit (A0-A2).
Claim 10
Dependent Claim
43 words
The method of Claim 9 further comprising the steps of: buffering and latching said address bits prior to said passing or blocking steps, decoding said passed or substituted address bits into an address, and accessing memory cells that correspond to the decoded address.
References Cited (Backward Citations)
No citation records indexed.
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