Differential interpolating switched capacitor filter and method

Claim 3

The method of claim 1 further comprising the step of gating said differential output from the output stage feeding back to an input to the input stage through a feedback capacitor at the first frequency in order to prevent the interpolated output from reaching the input stage.

Claim 4

The method of claim 2 further comprising the step of feeding forward said differential output from the input stage to said differential input to the amplifier through a circuit which has a third set of two parallel paths, a first path of said third set of two parallel paths with an ungated capacitor therein and a second path of said third set of two parallel paths with a gated capacitor therein which is gated at the first clocking frequency.

Claim 5

The method of claim 1 further comprising the step of feeding forward said differential output from the input stage to said differential input to the amplifier through a circuit which has a third set of two parallel paths, a first path of said third set of two parallel paths with an ungated capacitor therein and a second path of said third set of two parallel paths with a gated capacitor therein which is gated at the first clocking frequency.

Claim 6

A switched capacitor filter comprising: at least one input stage for operating at a first frequency; an output stage for providing an interpolated output at double the first frequency, said output stage comprising, an amplifier having two parallel paths connecting a differential input and respective opposite polarity output thereof, each of said two parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in each of said two parallel paths so that one said capacitor in one of said two parallel paths is charging and said capacitor in the other of said two parallel paths is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, and two further parallel paths each respectively connecting an output from said input stage to an input to said amplifier, each of said two further parallel paths having a further capacitor therein and switching means for switchably connecting said further capacitor in each of said two further parallel paths so that one said further capacitor in one of said two further parallel paths is charging and said further capacitor in the other of said two further parallel paths is discharging during the first clock phase and so that the charging and discharging are reversed in the second clock phase.

Claim 7

A switched capacitor filter comprising: at least one input stage for operating at a first frequency; an output stage for providing an interpolated output at double the first frequency, said output stage comprising, an amplifier having two parallel paths connecting a differential input and respective opposite polarity output thereof, each of said two parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in each of said two parallel paths so that one said capacitor in one of said two parallel paths is charging and said capacitor in the other of said two parallel paths is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, and two further parallel paths each respectively connecting an output from said input stage to an input to said amplifier, each of said two further parallel paths having a further capacitor therein and switching means for switchably connecting said further capacitor in each of said two further parallel paths so that one said further capacitor in one of said two further parallel paths is charging and said further capacitor in the other of said two further parallel paths is discharging during the first clock phase and so that the charging and discharging are reversed in the second clock phase.

Claim 8

The filter of claim 5 further comprising a feedback path for feeding back the interpolated output from said output stage to said input to said input stage, said feedback path having a feedback capacitor and means for gating said feedback capacitor at the first frequency in order to prevent the interpolated output from reaching said input stage.

Claim 9

The filter of claim 4 further comprising a feed forward path for feeding forward said output from said input stage to said input to said amplifier, said feed forward path comprising a first path with an ungated capacitor therein and a second path parallel to said first path which has a gated capacitor therein and switching means for gating said gated capacitor in said second path at the first clocking frequency.

Claim 10

The filter of claim 5 further comprising a feed forward path for feeding forward said output from said input stage to said input to said amplifier, said feed forward path comprising a first path with an ungated capacitor therein and a second path parallel to said first path which has a gated capacitor therein and switching means for gating said gated capacitor in said second path at the first clocking frequency.

Claim 11

An N stage (N being at least two), differential switched capacitor low pass filter for a telephone system CODEC comprising: N-1 serially connected input stages for operating at a first frequency; and an interpolating output stage for providing an interpolated output at double the first frequency, said output stage comprising, a differential amplifier having two pairs of parallel paths, each of said pairs connecting a differential input and respective opposite polarity differential output thereof, each of said parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in said each of said parallel paths so that one said capacitor is charging and the other is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, two further pairs of parallel paths, each of said further pairs connecting differential outputs from said input stages to said differential input to said amplifier, each of said further parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in each of said further parallel paths so that one said capacitor is charging and the other is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, two feedback paths, each of said feedback paths for feeding back said differential outputs from said output stage to inputs to said input stages, each of said feedback paths having a feedback capacitor and switching means for gating said feedback capacitor at the first frequency in order to prevent the interpolated output from reaching said input stage, and two feed forward paths, each of said feed forward paths for feeding forward said differential outputs from said input stages to said differential input to said amplifier, each of said feed forward paths comprising a first path with an ungated capacitor therein and a second path parallel to said first path which has a capacitor therein and switching means for gating said capacitor in said second path at the first clocking frequency.

Claim 12

An N stage (N being at least two), differential switched capacitor low pass filter for a telephone system CODEC comprising: N-1 serially connected input stages for operating at a first frequency; and an interpolating output stage for providing an interpolated output at double the first frequency, said output stage comprising, a differential amplifier having two pairs of parallel paths, each of said pairs connecting a differential input and respective opposite polarity differential output thereof, each of said parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in said each of said parallel paths so that one said capacitor is charging and the other is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, two further pairs of parallel paths, each of said further pairs connecting differential outputs from said input stages to said differential input to said amplifier, each of said further parallel paths having a capacitor therein and switching means for switchably connecting said capacitor in each of said further parallel paths so that one said capacitor is charging and the other is discharging during a first clock phase and so that the charging and discharging are reversed in a second clock phase, two feedback paths, each of said feedback paths for feeding back said differential outputs from said output stage to inputs to said input stages, each of said feedback paths having a feedback capacitor and switching means for gating said feedback capacitor at the first frequency in order to prevent the interpolated output from reaching said input stage, and two feed forward paths, each of said feed forward paths for feeding forward said differential outputs from said input stages to said differential input to said amplifier, each of said feed forward paths comprising a first path with an ungated capacitor therein and a second path parallel to said first path which has a capacitor therein and switching means for gating said capacitor in said second path at the first clocking frequency.

Claim 13

The filter of claim 9 wherein said capacitors in said parallel paths have substantially equal capacitances, and said capacitors in said further parallel paths have substantially equal capacitances.

Claim 14

The filter of claim 9 wherein each of said switching means comprises a field effect transistor.