Switched-capacitor interolation filter

Claim 2

An interpolation circuit for receiving a sampled input signal and producing an output signal that is sampled at twice the input signal sampling frequency and thereby providing a smoothing filtering effect that eliminates extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead, a noninverting input lead connected to ground, and an output lead; an input terminal for receiving said sampled input signal; a switched-capacitor input network connected between said inverting input lead and said input terminal, said network comprising a first and a second capacitor, said second capacitor having a predetermined fractional capacitance of said first capacitor; a first switch means connecting said first capacitor between said inverting input lead and said input terminal; a second switch means connecting said second capacitor between said inverting input lead and said input terminal, and a first clock and a second clock for controlling said first and said second switch means; and feedback means connected between said output lead and said inverting input lead, said feedback means cooperating with said input network to provide a sampled output signal at double the input signal sampling frequency and wherein every second output signal sample is equal to the input signal sample, and every other output signal sample is equal to a value interpolated from two adjacent input signal samples.

Claim 3

The circuit as described in claim 1 wherein said second capacitor of said input network has one-half the capacitance value as said first capacitor.

Claim 4

The circuit as described in claim 1 wherein said switch means are metal-oxide-silicon field effect transistors (MOSFETs) each having a gate electrode connected to one of said clocks.

Claim 5

An interpolation circuit for receiving a sampled input signal and producing an output signal that is sampled at twice the input signal sampling frequency and thereby providing a smoothing filtering effect that eliminates extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead, a non-inverting input lead connected to ground, and an output lead; an input terminal for receiving said sampled input signal; a first and a second clock means; a switched capacitor input network connected between said inverting input lead and said input terminal, said network comprising: a first capacitor having a first and a second plate; a first switch means connecting said first plate of said first capacitor to said input terminal; a second switch means connecting said second plate of said first capacitor to said inverting input lead; a first clock means for controlling said first and said second switch means; a third switch means connecting said first plate of said first capacitor to ground; a second clock means for controlling said third switch means; a second capacitor having a pre-determined fractional capacitance of said first capacitor, said second capacitor having a first and a second plate; a fourth switch means controlled by said first clock means, said fourth switch means being connected between said first plate of said second capacitor and said input terminal; a fifth switch means controlled by said second clock, said fifth switch means being connected between said first plate of said second capacitor and said inverting input lead; a sixth switch means controlled by said second clock means, said sixth switch means connected between said second plate of said second capacitor and said input terminal; a seventh switch means controlled by said first clock means, said seventh switch means connected between said second plate of said second capacitor and ground; and feedback means connected between said output lead and said inverting input lead, said feedback means cooperating with said input network to provide a sampled output signal at double the input signal sampling frequency and wherein every second output signal sample is equal to the input signal sample, and every other output signal sample is equal to a value interpolated from the two adjacent input signal samples.

Claim 6

An interpolation circuit for receiving a sampled input signal and producing an output signal that is sampled at twice the input signal sampling frequency and thereby providing a smoothing filtering effect that eliminates extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead, a non-inverting input lead connected to ground, and an output lead; an input terminal for receiving said sampled input signal; a first and a second clock means; a switched capacitor input network connected between said inverting input lead and said input terminal, said network comprising: a first capacitor having a first and a second plate; a first switch means connecting said first plate of said first capacitor to said input terminal; a second switch means connecting said second plate of said first capacitor to said inverting input lead; a first clock means for controlling said first and said second switch means; a third switch means connecting said first plate of said first capacitor to ground; a second clock means for controlling said third switch means; a second capacitor having a pre-determined fractional capacitance of said first capacitor, said second capacitor having a first and a second plate; a fourth switch means controlled by said first clock means, said fourth switch means being connected between said first plate of said second capacitor and said input terminal; a fifth switch means controlled by said second clock, said fifth switch means being connected between said first plate of said second capacitor and said inverting input lead; a sixth switch means controlled by said second clock means, said sixth switch means connected between said second plate of said second capacitor and said input terminal; a seventh switch means controlled by said first clock means, said seventh switch means connected between said second plate of said second capacitor and ground; and feedback means connected between said output lead and said inverting input lead, said feedback means cooperating with said input network to provide a sampled output signal at double the input signal sampling frequency and wherein every second output signal sample is equal to the input signal sample, and every other output signal sample is equal to a value interpolated from the two adjacent input signal samples.

Claim 7

An interpolation circuit for receiving a sampled input signal and producing an output signal that is sampled at twice the input signal sampling frequency and thereby providing a smoothing filtering effect that eliminates extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead, a non-inverting input lead connected to ground, and an output lead; an input terminal for receiving said sampled input signals; a switched capacitor input network connected between said inverting input lead and said input terminal, said network comprising: a first and a second capacitor, said second capacitor having a pre-determined fractional capacitance of said first capacitor; a first switch means for connecting said first capacitor between said inverting input lead and said input terminal; a second switch means for connecting said second capacitor between said inverting input lead and said input terminal; first and second clock means for controlling said first and second switch means; and feedback means connected between said output lead and said inverting input lead, said feedback means comprising: a third capacitor connected between said inverting input lead and said output lead; a third switch means controlled by said second clock, said third switch means connected between said second plate of said first capacitor and said output lead; a fourth capacitor having a first plate and a second plate, said second plate of said fourth capacitor connected to ground; a fourth switch means controlled by said first clock, said fourth switch means connected between said output lead and said first plate of said fourth capacitor; and a fifth switch means controlled by said second clock, said fifth switch means connected between said first plate of said fourth capacitor and said inverting input lead, wherein said feedback means cooperates with said input network to provide a sampled output signal at double the input signal sampling frequency and wherein every second output signal sample is equal to the input signal sample, and every other output signal sample is equal to a value interpolated from the two adjacent input signal samples.

Claim 8

An interpolation circuit for receiving a sampled input signal and producing an output signal that is sampled at twice the input signal sampling frequency and thereby providing a smoothing filtering effect that eliminates extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead, a non-inverting input lead connected to ground, and an output lead; an input terminal for receiving said sampled input signals; a switched capacitor input network connected between said inverting input lead and said input terminal, said network comprising: a first and a second capacitor, said second capacitor having a pre-determined fractional capacitance of said first capacitor; a first switch means for connecting said first capacitor between said inverting input lead and said input terminal; a second switch means for connecting said second capacitor between said inverting input lead and said input terminal; first and second clock means for controlling said first and second switch means; and feedback means connected between said output lead and said inverting input lead, said feedback means comprising: a third capacitor connected between said inverting input lead and said output lead; a third switch means controlled by said second clock, said third switch means connected between said second plate of said first capacitor and said output lead; a fourth capacitor having a first plate and a second plate, said second plate of said fourth capacitor connected to ground; a fourth switch means controlled by said first clock, said fourth switch means connected between said output lead and said first plate of said fourth capacitor; and a fifth switch means controlled by said second clock, said fifth switch means connected between said first plate of said fourth capacitor and said inverting input lead, wherein said feedback means cooperates with said input network to provide a sampled output signal at double the input signal sampling frequency and wherein every second output signal sample is equal to the input signal sample, and every other output signal sample is equal to a value interpolated from the two adjacent input signal samples.

Claim 9

An interpolation circuit for receiving a sampled input signal and producing a filtered output signal that is sampled at twice the input signal sampling frequency, thereby eliminating extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead and an output lead; an input terminal for receiving said sampled input signal; a first capacitor having a first and a second plate; a first switch means connecting said first plate of said first capacitor to said input terminal; a second switch means connecting said second plate of said first capacitor to said inverting input lead; a first clock means for controlling said first and said second switch means; a third switch means connecting said first plate of said first capacitor to ground; a second clock means for controlling said third switch means; a second capacitor having a pre-determined fractional capacitance of said first capacitor, said second capacitor having a first and a second plate; a fourth switch means controlled by said first clock means, said fourth switch means being connected between said first plate of said second capacitor and said input terminal; a fifth switch means controlled by said second clock, said fifth switch means being connected between said first plate of said second capacitor and said inverting input lead; a sixth switch means controlled by said second clock means, said sixth switch means connected between said second plate of said second capacitor and said input terminal; a seventh switch means controlled by said first clock means, said seventh switch means connected between said second plate of said second capacitor and ground; a third capacitor being connected between said inverting input lead and said output lead; an eighth switch means controlled by said second clock, said eighth switch means connected between said second plate of said first capacitor and said output lead; a fourth capacitor having a first plate and a second plate, said second plate of said fourth capacitor connected to ground; a ninth switch means controlled by said first clock, said ninth switch means being connected between said output lead and said first plate of said fourth capacitor; and a tenth switch means controlled by said second clock, said tenth switch means being connected between said first plate of said fourth capacitor and said inverting input lead.

Claim 10

An interpolation circuit for receiving a sampled input signal and producing a filtered output signal that is sampled at twice the input signal sampling frequency, thereby eliminating extraneous output signal components around the input signal sampling frequency, said circuit comprising: an operational amplifier having an inverting input lead and an output lead; an input terminal for receiving said sampled input signal; a first capacitor having a first and a second plate; a first switch means connecting said first plate of said first capacitor to said input terminal; a second switch means connecting said second plate of said first capacitor to said inverting input lead; a first clock means for controlling said first and said second switch means; a third switch means connecting said first plate of said first capacitor to ground; a second clock means for controlling said third switch means; a second capacitor having a pre-determined fractional capacitance of said first capacitor, said second capacitor having a first and a second plate; a fourth switch means controlled by said first clock means, said fourth switch means being connected between said first plate of said second capacitor and said input terminal; a fifth switch means controlled by said second clock, said fifth switch means being connected between said first plate of said second capacitor and said inverting input lead; a sixth switch means controlled by said second clock means, said sixth switch means connected between said second plate of said second capacitor and said input terminal; a seventh switch means controlled by said first clock means, said seventh switch means connected between said second plate of said second capacitor and ground; a third capacitor being connected between said inverting input lead and said output lead; an eighth switch means controlled by said second clock, said eighth switch means connected between said second plate of said first capacitor and said output lead; a fourth capacitor having a first plate and a second plate, said second plate of said fourth capacitor connected to ground; a ninth switch means controlled by said first clock, said ninth switch means being connected between said output lead and said first plate of said fourth capacitor; and a tenth switch means controlled by said second clock, said tenth switch means being connected between said first plate of said fourth capacitor and said inverting input lead.

Claim 11

Structure as in claim 6 wherein said first, third, and fourth capacitors are of equal capacitance values twice the capacitance value of said second capacitor.

Claim 12

Structure as in claim 6 wherein each of said switch means comprises a MOSFET device.