US5495200A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Double sampled biquad switched capacitor filter
Assignee: Analog Devices Inc
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Filing: 1993-04-06
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Granted: 1996-02-27
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Expires: 2013-04-06
Abstract
Abstract A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.
Inventors
- 👤 Tom W. Kwan
- 👤 Paul F. Ferguson, Jr.
- 👤 Wai L. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:03
CPC Classifications
H; H03; H03H; H03H19/00; H03H19/004
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
185 words
A biquad switched capacitor filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving an analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
Claim 2
Dependent Claim
185 words
A biquad switched capacitor filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving an analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
Claim 3
Dependent Claim
153 words
A biquad switched capacitor filter as defined in claim 1 further including a third stage including a third operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said third operational amplifier; a third cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a third pair of capacitors on said first and second clock phases and for coupling charge from said third pair of capacitors to the inputs of said third operational amplifier on said first clock phase; and a fourth cross-coupled switched capacitor circuit for coupling charge from the outputs of said third operational amplifier to a fourth pair of capacitors on said first and second clock phases and for coupling charge from said fourth pair of capacitors to the inputs of said second operational amplifier on said second clock phase.
Claim 4
Dependent Claim
54 words
A biquad switched capacitor filter as defined in claim 1 wherein each of said cross-coupled switched capacitor circuits includes means for coupling an input voltage to said pair of capacitors during one clock phase and means for coupling said input voltage with reversed polarity to said pair of capacitors during the other clock phase.
Claim 5
Dependent Claim
23 words
A biquad switched capacitor filter as defined in claim 1 wherein each of said cross-coupled switched capacitor circuits is implemented with CMOS transistors.
Claim 6
Dependent Claim
110 words
A biquad switched capacitor filter as defined in claim 1 wherein each of said cross-coupled switched capacitor circuits includes a first switch connected between a positive input and a first capacitor of said pair of capacitors, a second switch connected between a negative input and a second capacitor of said pair of capacitors, a third switch connected between said positive input and said second capacitor, and a fourth switch connected between said negative input and said first capacitor, said first and second switches being closed in response to one of said clock phases and said third and fourth switches being closed in response to the other of said clock phases.
Claim 7
Dependent Claim
201 words
In combination: A one-bit digital-to-analog converter for converting a data stream to an analog signal; and a biquad switched capacitor filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving said analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
Claim 8
Dependent Claim
201 words
In combination: A one-bit digital-to-analog converter for converting a data stream to an analog signal; and a biquad switched capacitor filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving said analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
Claim 9
Dependent Claim
72 words
The combination as defined in claim 6 wherein said one-bit digital-to-analog converter comprises a cross-coupled switched capacitor circuit including a pair of capacitors, switching means for coupling charge from a reference source to said pair of capacitors during said first and second clock phases and switching means for coupling charge from said pair of capacitors to said biquad switched capacitor filter during said second clock phase using data dependent switch control signals.
Claim 10
Dependent Claim
156 words
The combination as defined in claim 6 wherein said biquad switched capacitor filter further includes: a third stage including a third operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said third operational amplifier; a third cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a third pair of capacitors on said first and second clock phases and for coupling charge from said third pair of capacitors to the inputs of said third operational amplifier on said first clock phase; and a fourth cross-coupled switched capacitor circuit for coupling charge from the outputs of said third operational amplifier to a fourth pair of capacitors on said first and second clock phases and for coupling charge from said fourth pair of capacitors to the inputs of said second operational amplifier on said second clock phase.
Claim 11
Dependent Claim
51 words
The combination as defined in claim 6 wherein each of said cross-coupled switched capacitor circuits includes means for coupling an input voltage to said pair of capacitors during one clock phase and means for coupling said input voltage with reversed polarity to said pair of capacitors during the other clock phase.
Claim 12
Dependent Claim
20 words
The combination as defined in claim 6 wherein each of said cross-coupled switched capacitor circuits is implemented with CMOS transistors.
Claim 13
Dependent Claim
251 words
A sigma delta digital-to-analog converter comprising: an interpolation filter for increasing the rate of an input digital signal to provide a high data rate digital signal; a sigma delta modulator for converting the high data rate digital signal to a one-bit signal with shaped quantization noise and providing a modulator output; a one-bit digital-to-analog converter for converting the modulator output to an analog signal; and a biquad switched capacitor output filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving said analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
Claim 14
Dependent Claim
251 words
A sigma delta digital-to-analog converter comprising: an interpolation filter for increasing the rate of an input digital signal to provide a high data rate digital signal; a sigma delta modulator for converting the high data rate digital signal to a one-bit signal with shaped quantization noise and providing a modulator output; a one-bit digital-to-analog converter for converting the modulator output to an analog signal; and a biquad switched capacitor output filter comprising: a first stage including a first operational amplifier having inverting and noninverting inputs for receiving said analog signal, and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said first operational amplifier; a second stage including a second operational amplifier having inverting and noninverting inputs and positive and negative outputs, and feedback capacitors connected between said outputs and opposite polarity inputs of said second operational amplifier; a first cross-coupled switched capacitor circuit for coupling charge from the outputs of said first operational amplifier to a first pair of capacitors on first and second clock phases and for coupling charge from said first pair of capacitors to the inputs of said second operational amplifier on said second clock phase; and a second cross-coupled switched capacitor circuit for coupling charge from the outputs of said second operational amplifier to a second pair of capacitors on said first and second clock phases and for coupling charge from said second pair of capacitors to the inputs of said first operational amplifier on said first clock phase.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |