US5679607A
Expired / Lapsed
US
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Method of manufacturing a damage free buried contact using salicide technology
Assignee: Winbond Electronics Corp
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Filing: 1995-08-11
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Granted: 1997-10-21
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Expires: 2015-08-11
Abstract
Abstract A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.
Inventors
- 👤 Ming-Hsi Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:26
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; Y; Y10; Y10S; Y10S438/00; Y10S438/934
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
92 words
A method of manufacturing a semiconductor cell with at least one buried contact, comprising the steps of: a) forming an oxide layer on a substrate, b) forming a polysilicon region on said oxide layer, c) etching a cavity in said oxide layer between a portion of said polysilicon region and said substrate, d) forming a buried contact region within said substrate, such that a portion of said buried contact region underlies said cavity, e) forming a continuous metal layer on said polysilicon region, within said cavity, and on said buried contact region.
Claim 2
Independent Claim
92 words
A method of manufacturing a semiconductor cell with at least one buried contact, comprising the steps of: a) forming an oxide layer on a substrate, b) forming a polysilicon region on said oxide layer, c) etching a cavity in said oxide layer between a portion of said polysilicon region and said substrate, d) forming a buried contact region within said substrate, such that a portion of said buried contact region underlies said cavity, e) forming a continuous metal layer on said polysilicon region, within said cavity, and on said buried contact region.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said step (e) further comprises: reacting said metal layer with said polysilicon and buried contact region to form a silicide layer.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said oxide layer has a thickness range of 70 to 300 Å.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein said polysilicon region has a thickness range of 1,500 to 5,000 Å.
Claim 6
Dependent Claim
29 words
The method of claim 1 wherein said step (b) further comprises the step of: doping said polysilicon region with phosphorous oxychloride to reduce the resistance of said polysilicon region.
Claim 7
Dependent Claim
24 words
The method of claim 1 wherein said step (b) further comprises the step of: anisotropically etching said polysilicon region without etching said oxide layer.
Claim 8
Dependent Claim
23 words
The method of claim 1 wherein said step (c) further comprises the step of: isotropically etching said oxide layer with an HF-based solution.
Claim 9
Dependent Claim
43 words
The method of claim 1 wherein said step (d) further comprises the step of: implanting ions into said substrate with an energy in the range of 5-100 kev, and a dosage in the range of 10 15 to 8×10 15 ions/cm 2 .
Claim 10
Dependent Claim
19 words
The method of claim 8 wherein said ions are chosen from the group consisting of arsenic and phosphorus ions.
Claim 11
Dependent Claim
29 words
The method of claim 1 wherein said step (e) further comprises the step of: forming said metal layer with a thickness in the range of 300 to 1,800 Å.
Claim 12
Dependent Claim
25 words
The method of claim 2 wherein step (e) further comprises: using rapid thermal annealing with a temperature range of 500°-1000° C. and N 2 gas.
Claim 13
Dependent Claim
33 words
The method of claim 2 wherein said silicide layer is converted from C49 TiSi 2 with a resistance value of 60-80 μΩcm to C54 TiSi 2 with a resistance value of 16-20 μΩcm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |