US5053349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for interconnecting semiconductor devices
Assignee: Toshiba Corp
•
Filing: 1989-06-02
•
Granted: 1991-10-01
•
Expires: 2009-06-02
Abstract
Abstract There is disclosed a method for the production of semiconductor devices, which has a process for forming an active region and isolation region on a semiconductor substrate, a gate dioxide layer on both active and isolating regions, and a gate electrode on the active region and an interconnection on the isolation region respectively, by patterning a conductive layer after the conductive layer is piled on the gate dioxide layer; a process for forming a diffused region on the active region by patterning through the gate electrode and interconnection as masks, and an inter-level dioxide layer on a pattern formed surface of these regions; a process for forming holes for directly connecting the diffused layer with interconnection and interconnecting the interconnection by partially and selectively eliminating the inter-level dioxide layer; and a process for selectively forming metal layers at bottoms of the holes.
Inventors
- 👤 Fumitomo Matsuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10W20/01; H10W20/031; H10W20/056; H10W20/0698
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
218 words
A method of manufacturing semiconductor devices, comprising a first step of forming an active region and an isolation region on a semiconductor substrate; a second step of forming a gate dioxide layer having a predetermined thickness on said active region and said isolation region; a third step of forming a gate electrode on said active region, and an interconnection at a predetermined portion on said isolation region by stacking a conductive layer on said gate dioxide layer and patterning the conductive layer so that a predetermined pattern is formed; a fourth step of forming a diffusional region on said active region through masking using said gate electrode and interconnection; a fifth step of forming an inter-level dioxide layer on a pattern-formed surface of said semiconductor substrate having said predetermined pattern formed by said third step; a sixth step of forming at the same time a first connection hole for directly connecting said diffusional region with said interconnection and a second connection hole for connecting a plurality of interconnections to each other, respectively, by partially and selectively eliminating said inter-level dioxide layer; and a seventh step of selectively forming a metal layer at the bottoms of said first and second connection holes and having a predetermined thickness which is thicker than said predetermined thickness of said gate dioxide layer.
Claim 2
Independent Claim
218 words
A method of manufacturing semiconductor devices, comprising a first step of forming an active region and an isolation region on a semiconductor substrate; a second step of forming a gate dioxide layer having a predetermined thickness on said active region and said isolation region; a third step of forming a gate electrode on said active region, and an interconnection at a predetermined portion on said isolation region by stacking a conductive layer on said gate dioxide layer and patterning the conductive layer so that a predetermined pattern is formed; a fourth step of forming a diffusional region on said active region through masking using said gate electrode and interconnection; a fifth step of forming an inter-level dioxide layer on a pattern-formed surface of said semiconductor substrate having said predetermined pattern formed by said third step; a sixth step of forming at the same time a first connection hole for directly connecting said diffusional region with said interconnection and a second connection hole for connecting a plurality of interconnections to each other, respectively, by partially and selectively eliminating said inter-level dioxide layer; and a seventh step of selectively forming a metal layer at the bottoms of said first and second connection holes and having a predetermined thickness which is thicker than said predetermined thickness of said gate dioxide layer.
Claim 3
Dependent Claim
37 words
A method according to claim 1; wherein said metal layer is selectively formed against a remaining portion of said inter-level dioxide layer by means of a chemical vapor deposition (CVD) of tungsten (W) in said step process.
Claim 4
Dependent Claim
43 words
A method according to claim 1; wherein said metal layer is selectively formed against a remaining portion of said inter-level dioxide layer by means of selective silification of titanium (Ti) silicide by heat treatment after forming a Ti layer in said seventh step.
Claim 5
Dependent Claim
34 words
A method according to claim 1; wherein said gate electrode is formed of a poly-crystal silicon and a metal having a high fusion point as materials in said second process to said third step.
Claim 6
Dependent Claim
37 words
A method according to claim 1; wherein said gate electrode is formed using poly-crystal silicon and metal silicide as materials, in which said metal has a high fusion point, in said second process to said third step.
Claim 7
Dependent Claim
27 words
A method according to claim 1; wherein said gate electrode is formed using tungsten silicide (WSi) as the material in said second step to said third step.
References Cited (Backward Citations)
US3889359A
Cited
US4072545A
Cited
US4102733A
Cited
US4412237A
Cited
US4413403A
Cited
US4392150A
Cited
US4462149A
Cited
GB2151847A
Cited
US4682403A
Cited
US4892845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-30 | 1995-04-01 | 1995-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-30 | 1999-04-01 | 1999-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-30 | 2003-04-01 | 2003-10-01 | $7700.00 | Window Closed / Lapsed |