Method for fabricating multi-level interconnection structure for semiconductor device

Claim 1

A method for fabricating a semiconductor device having a multi-level interconnection structure, said method comprising the steps of: forming an insulating layer on a semiconductor substrate; forming an interconnect metal film on said insulating layer; forming, on an entire surface of said interconnect metal film, a first insulating film having a first polishing rate in a chemical mechanical polishing process; sequentially and selectively etching said first insulating film and said interconnect metal film to form a lower interconnect; forming, on an entire resulting surface, a second insulating film having a second polishing rate higher than said first polishing rate of said first insulating film, so that said lower interconnect and said first insulating film which remains on said lower interconnect are completely buried in said second insulating film; lapping down a surface of said second insulating film by the chemical mechanical polishing process using said first insulating film as a stopper thereby forming a planarized surface of said first and second insulating films; planarizing said lower interconnect and said second insulating film; and forming a third insulating film on said planarized surface of said first and second insulating films.

Claim 2

A method for fabricating a semiconductor device having a multi-level interconnection structure, said method comprising the steps of: forming an insulating layer on a semiconductor substrate; forming an interconnect metal film on said insulating layer; forming, on an entire surface of said interconnect metal film, a first insulating film having a first polishing rate in a chemical mechanical polishing process; sequentially and selectively etching said first insulating film and said interconnect metal film to form a lower interconnect; forming, on an entire resulting surface, a second insulating film having a second polishing rate higher than said first polishing rate of said first insulating film, so that said lower interconnect and said first insulating film which remains on said lower interconnect are completely buried in said second insulating film; lapping down a surface of said second insulating film by the chemical mechanical polishing process using said first insulating film as a stopper thereby forming a planarized surface of said first and second insulating films; planarizing said lower interconnect and said second insulating film; and forming a third insulating film on said planarized surface of said first and second insulating films.

Claim 10

A method for fabricating a semiconductor device having a multi-level interconnection structure, said method comprising the steps of: forming an insulating layer on a semiconductor substrate; forming an interconnect metal film on said insulating layer; forming, on an entire surface of said interconnect metal film, a first insulating film having a first polishing rate in a chemical mechanical polishing process; sequentially and selectively etching said first insulating film and said interconnect metal film to form a lower interconnect; forming, on an entire resulting surface, a second insulating film having a second polishing rate higher than said first polishing rate of said first insulating film, so that said lower interconnect and said first insulating film which remains on said lower interconnect are completely buried in said second insulating film; lapping down a surface of said second insulating film by the chemical mechanical polishing process using said first insulating film as a stopper thereby forming a planarized surface of said first and second insulating films; etching a surface of said first insulating film and a surface of said second insulating film under a condition of etching rates common to both said surfaces so that said first insulating film on said lower interconnect is removed to thereby form a planarized surface of said second insulating film and said lower interconnect; and forming a third insulating film on said planarized surface of said second insulating film and said lower interconnect.

Claim 11

A method for fabricating a semiconductor device having a multi-level interconnection structure, said method comprising the steps of: forming an insulating layer on a semiconductor substrate; forming an interconnect metal film on said insulating layer; forming, on an entire surface of said interconnect metal film, a first insulating film having a first polishing rate in a chemical mechanical polishing process; sequentially and selectively etching said first insulating film and said interconnect metal film to form a lower interconnect; forming, on an entire resulting surface, a second insulating film having a second polishing rate higher than said first polishing rate of said first insulating film, so that said lower interconnect and said first insulating film which remains on said lower interconnect are completely buried in said second insulating film; lapping down a surface of said second insulating film by the chemical mechanical polishing process using said first insulating film as a stopper thereby forming a planarized surface of said first and second insulating films; etching a surface of said first insulating film and a surface of said second insulating film under a condition of etching rates common to both said surfaces so that said first insulating film on said lower interconnect is removed to thereby form a planarized surface of said second insulating film and said lower interconnect; and forming a third insulating film on said planarized surface of said second insulating film and said lower interconnect.