Extended chip select reset apparatus and method

Claim 1

An apparatus for generating a reset signal for a subscriber line audio processing circuit (SLAC), comprising: a first input port for reading in a clock signal including a plurality of clock pulses; a second input port for reading in a chip select signal, the chip select signal being in one of an active state and an inactive state; a reset circuit, said reset circuit generating the reset signal when the chip select signal is in the active state for at least a predetermined number of the plurality of clock pulses, wherein the predetermined number of clock pulses is greater than a number of clock pulses needed to read in a digital command by the SLAC; and a third input port for reading in an externally-generated reset signal, the externally-generated reset signal being in one of an active state and an inactive state, the reset signal also being generated when the externally-generated reset signal is placed in the active state.

Claim 2

An apparatus for generating a reset signal for a subscriber line audio processing circuit (SLAC), comprising: a first input port for reading in a clock signal including a plurality of clock pulses; a second input port for reading in a chip select signal, the chip select signal being in one of an active state and an inactive state; a reset circuit, said reset circuit generating the reset signal when the chip select signal is in the active state for at least a predetermined number of the plurality of clock pulses, wherein the predetermined number of clock pulses is greater than a number of clock pulses needed to read in a digital command by the SLAC; and a third input port for reading in an externally-generated reset signal, the externally-generated reset signal being in one of an active state and an inactive state, the reset signal also being generated when the externally-generated reset signal is placed in the active state.

Claim 9

An apparatus for generating a reset signal for a device which receives n-bit digital commands, said apparatus receiving a chip select signal and a clock signal which includes a plurality of clock pulses, said apparatus comprising: a timing circuit, the timing circuit determining when the chip select signal is placed into an asserted state from an unasserted state and outputting a first signal as a result thereof, the timing circuit determining when the chip select signal is placed into the unasserted state from the asserted state and outputting a second signal as a result thereof; a counting circuit, counting a number of clock pulses of the clock signal for a time period between receipt of the first signal from the timing circuit and receipt of the second signal from the timing circuit; and a reset generation circuit, the reset generating circuit generating the reset signal and outputting the reset signal to the device if the number of clock pulses counted by the counting circuit exceeds a predetermined value, the predetermined value being greater than the number n.

Claim 10

An apparatus for generating a reset signal for a device which receives n-bit digital commands, said apparatus receiving a chip select signal and a clock signal which includes a plurality of clock pulses, said apparatus comprising: a timing circuit, the timing circuit determining when the chip select signal is placed into an asserted state from an unasserted state and outputting a first signal as a result thereof, the timing circuit determining when the chip select signal is placed into the unasserted state from the asserted state and outputting a second signal as a result thereof; a counting circuit, counting a number of clock pulses of the clock signal for a time period between receipt of the first signal from the timing circuit and receipt of the second signal from the timing circuit; and a reset generation circuit, the reset generating circuit generating the reset signal and outputting the reset signal to the device if the number of clock pulses counted by the counting circuit exceeds a predetermined value, the predetermined value being greater than the number n.

Claim 11

An apparatus for generating a reset signal for a device which receives n-bit digital commands, said apparatus receiving a chip select signal and a clock signal which includes a plurality of clock pulses, said apparatus comprising: a timing circuit, the timing circuit determining when the chip select signal is placed into an asserted state from an unasserted state and outputting a first signal as a result thereof, the timing circuit determining when the chip select signal is placed into the unasserted state from the asserted state and outputting a second signal as a result thereof; a counting circuit, the counting circuit being connected to the timing circuit, the counting circuit counting a number of clock pulses of the clock signal for a time period between receipt of the first signal from the timing circuit and receipt of the second signal from the timing circuit; and a reset generation circuit, the reset generation circuit being connected to the counting circuit, the reset generation circuit generating the reset signal and outputting the reset signal to the device if the number of clock pulses counted by the counting circuit exceeds a predetermined value, the predetermined value being greater than the number n, said apparatus further receiving an externally-generated reset signal in one of an active state and an inactive state, and the reset signal also being generated when the externally-generated reset signal is placed into the active state.

Claim 12

An apparatus for generating a reset signal for a device which receives n-bit digital commands, said apparatus receiving a chip select signal and a clock signal which includes a plurality of clock pulses, said apparatus comprising: a timing circuit, the timing circuit determining when the chip select signal is placed into an asserted state from an unasserted state and outputting a first signal as a result thereof, the timing circuit determining when the chip select signal is placed into the unasserted state from the asserted state and outputting a second signal as a result thereof; a counting circuit, the counting circuit being connected to the timing circuit, the counting circuit counting a number of clock pulses of the clock signal for a time period between receipt of the first signal from the timing circuit and receipt of the second signal from the timing circuit; and a reset generation circuit, the reset generation circuit being connected to the counting circuit, the reset generation circuit generating the reset signal and outputting the reset signal to the device if the number of clock pulses counted by the counting circuit exceeds a predetermined value, the predetermined value being greater than the number n, said apparatus further receiving an externally-generated reset signal in one of an active state and an inactive state, and the reset signal also being generated when the externally-generated reset signal is placed into the active state.

Claim 17

A method for generating a reset signal for a device which receives n-bit digital commands, said device receiving a chip select signal and a clock signal which includes a plurality of clock pulses, the method comprising the steps of: a) determining when the chip select signal is placed into an unasserted state from an asserted state and outputting a first signal as a result thereof; b) determining when the chip select signal is placed into the asserted state from the unasserted state and outputting a second signal as a result thereof; c) counting a number of clock pulses of the clock signal for a time period between outputting the first signal and outputting the second signal; d) outputting the reset signal to the device if the number of clock pulses counted during the counting step c) is greater than a predetermined value, wherein the predetermined value is greater than the number n; e) receiving an externally generated reset signal which can be in one of a first state and a second state, said first state being indicative of a reset condition for said device; and f) outputting the reset signal to the device when the externally generated reset signal is in the first state.

Claim 18

A method for generating a reset signal for a device which receives n-bit digital commands, said device receiving a chip select signal and a clock signal which includes a plurality of clock pulses, the method comprising the steps of: a) determining when the chip select signal is placed into an unasserted state from an asserted state and outputting a first signal as a result thereof; b) determining when the chip select signal is placed into the asserted state from the unasserted state and outputting a second signal as a result thereof; c) counting a number of clock pulses of the clock signal for a time period between outputting the first signal and outputting the second signal; d) outputting the reset signal to the device if the number of clock pulses counted during the counting step c) is greater than a predetermined value, wherein the predetermined value is greater than the number n; e) receiving an externally generated reset signal which can be in one of a first state and a second state, said first state being indicative of a reset condition for said device; and f) outputting the reset signal to the device when the externally generated reset signal is in the first state.