US4857760A
Expired / Lapsed
US
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Bipolar glitch detector circuit
Assignee: Tektronix Inc
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Filing: 1988-02-10
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Granted: 1989-08-15
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Expires: 2008-02-10
Abstract
Abstract A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal includes a first monostable circuit for generating a first pulse having a duration equal to the predetermined maximum duration when a positive-going edge of a pulse occurs in the input signal. A second monostable circuit is provided for generating a second pulse also having a duration equal to the predetermined maximum duration when a negative-going edge of a pulse occurs in the input signal. An AND gate is coupled to the output of the first and second monostable circuits for generating a signal having a third pulse equal to the period of time both of the first and second pulses occur simultaneously. A flip-flop is coupled to the output of the AND gate for generating an output signal of a first logic state when the third pulse is generated. The flip-flop is also responsive to an external reset signal for setting the output signal at a second logic state when it is desired to detect further pulses in the input signal.
Inventors
- 👤 Carlton Stuebing
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:47
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
162 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: a first monostable circuit for generating a first pulse having a duration equal to the predetermined maximum duration when a positive-going edge of a pulse occurs in the input signal; a second monostable circuit for generating a second pulse also having a duration equal to the predetermined maximum duration when a negative-going edge of a pulse occurs in the input signal; AND gate means coupled to said first and second monostable circuits for generating a signal having a third pulse equal to the period of time both of said first and second pulses are present; and flip-flop means coupled to the output of said AND gate means for generating an output signal of a first logic state when the third pulse is generated, said flip-flop means also being responsive to an external reset signal for setting the output signal at a second logic state.
Claim 2
Dependent Claim
162 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: a first monostable circuit for generating a first pulse having a duration equal to the predetermined maximum duration when a positive-going edge of a pulse occurs in the input signal; a second monostable circuit for generating a second pulse also having a duration equal to the predetermined maximum duration when a negative-going edge of a pulse occurs in the input signal; AND gate means coupled to said first and second monostable circuits for generating a signal having a third pulse equal to the period of time both of said first and second pulses are present; and flip-flop means coupled to the output of said AND gate means for generating an output signal of a first logic state when the third pulse is generated, said flip-flop means also being responsive to an external reset signal for setting the output signal at a second logic state.
Claim 3
Dependent Claim
155 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: a positive edge triggered monostable circuit for sensing the positive-going edge of an input signal pulse and for generating a pulse having a duration equal to the predetermined maximum duration; a negative edge triggered monostable circuit for sensing the negative-going edge of an input signal pulse and for generating a pulse having a duration equal to the predetermined maximum duration; and AND gate means coupled to both of said positive and negative edge triggered monostable circuits for generating a pulse having a duration equal to the period of time when pulses from the positive and the negative edge triggered monostable circuit are present, wherein the pulse produced by the AND gate means is an output signal indicative of when a positive-going edge and a negative-going edge of an input signal pulse occur within the predetermined maximum duration.
Claim 4
Dependent Claim
155 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: a positive edge triggered monostable circuit for sensing the positive-going edge of an input signal pulse and for generating a pulse having a duration equal to the predetermined maximum duration; a negative edge triggered monostable circuit for sensing the negative-going edge of an input signal pulse and for generating a pulse having a duration equal to the predetermined maximum duration; and AND gate means coupled to both of said positive and negative edge triggered monostable circuits for generating a pulse having a duration equal to the period of time when pulses from the positive and the negative edge triggered monostable circuit are present, wherein the pulse produced by the AND gate means is an output signal indicative of when a positive-going edge and a negative-going edge of an input signal pulse occur within the predetermined maximum duration.
Claim 5
Dependent Claim
158 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: means for sensing the positive-going edge of an input signal pulse; means for sensing the negative-going edge of an input signal pulse; and means coupled to both of said positive-going and negative-going edge sensing means for generating an output signal indicative of when a positive-going edge and a negative-going edge of an input signal pulse occur within a predetermined period of time equal to the predetermined maximum duration, wherein said output signal has a first logic state prior to the occurrence of a positive-going edge and a negative-going edge within the predetermined period of time, and has a second logic state after the occurrence of a positive-going edge and a negative-going edge within the predetermined period of time, and wherein said generating means is responsive to an external reset signal for resetting said output signal to said first logic state.
Claim 6
Dependent Claim
158 words
A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal comprising: means for sensing the positive-going edge of an input signal pulse; means for sensing the negative-going edge of an input signal pulse; and means coupled to both of said positive-going and negative-going edge sensing means for generating an output signal indicative of when a positive-going edge and a negative-going edge of an input signal pulse occur within a predetermined period of time equal to the predetermined maximum duration, wherein said output signal has a first logic state prior to the occurrence of a positive-going edge and a negative-going edge within the predetermined period of time, and has a second logic state after the occurrence of a positive-going edge and a negative-going edge within the predetermined period of time, and wherein said generating means is responsive to an external reset signal for resetting said output signal to said first logic state.
References Cited (Backward Citations)
US2794123A
Cited
US3408581A
Cited
US3996586A
Cited
US4318047A
Cited
US4197502A
Cited
US4531223A
Cited
US4353032A
Cited
US4342965A
Cited
US4495621A
Cited
US4497068A
Cited
US4495642A
Cited
US4567601A
Cited
US4529892A
Cited
US4694200A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-14 | 1993-02-13 | 1993-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-14 | 1997-02-13 | 1997-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-14 | 2001-02-13 | 2001-08-15 | $7700.00 | Window Closed / Lapsed |