US5537055A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for protecting an ASIC by resetting it after a predetermined time period
Assignee: Microsemi Storage Solutions Ltd
•
Filing: 1994-06-30
•
Granted: 1996-07-16
•
Expires: 2014-06-30
Abstract
Abstract A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.
Inventors
- 👤 Graham B. Smith
- 👤 Charles K. Huscroft
- 👤 Vernon R. Little
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
A design protection circuit for a logic circuit comprising a counter for receiving clock pulses with said logic circuit and means for resetting the logic circuit said counter counting predetermined number of clock pulses, said predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function, external means for resetting the counter and the logic circuit at substantially the same time, the logic circuit being comprised of a reset node, and an OR gate having one input for receiving an internal reset signal from the counter and an external reset signal at another input, its output being connected to the reset node of the logic circuit, whereby the logic circuit may be reset by either the internal reset signal or the external reset signal.
Claim 2
Dependent Claim
136 words
A design protection circuit for a logic circuit comprising a counter for receiving clock pulses with said logic circuit and means for resetting the logic circuit said counter counting predetermined number of clock pulses, said predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function, external means for resetting the counter and the logic circuit at substantially the same time, the logic circuit being comprised of a reset node, and an OR gate having one input for receiving an internal reset signal from the counter and an external reset signal at another input, its output being connected to the reset node of the logic circuit, whereby the logic circuit may be reset by either the internal reset signal or the external reset signal.
Claim 3
Dependent Claim
40 words
A circuit as defined in claim 1 including means for setting and clearing higher order bits in the counter during testing of the logic circuit and prior to reaching a clock count to those higher order bite by the counter.
Claim 4
Dependent Claim
17 words
A circuit as defined in claim 1 in which the logic circuit is implemented in an ASIC.
Claim 5
Dependent Claim
33 words
A circuit as defined in claim 1 in which the counter is at least a 33 bit counter for counting in excess of 2 billion clock pulses before generating the internal reset signal.
Claim 6
Dependent Claim
112 words
A design protection circuit for a logic circuit comprising a counter for receiving clock pulses with said logic circuit and means for resetting the logic circuit upon said counter counting a predetermined number of clock pulses, said predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function, external means for resetting the counter and the logic circuit at substantially the same time, the logic circuit being comprised of a test mode output, means for inverting a test mode output signal and logically ANDing it with the clock pulses prior to application of the clock pulses to the logic circuit.
Claim 7
Dependent Claim
112 words
A design protection circuit for a logic circuit comprising a counter for receiving clock pulses with said logic circuit and means for resetting the logic circuit upon said counter counting a predetermined number of clock pulses, said predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function, external means for resetting the counter and the logic circuit at substantially the same time, the logic circuit being comprised of a test mode output, means for inverting a test mode output signal and logically ANDing it with the clock pulses prior to application of the clock pulses to the logic circuit.
Claim 8
Dependent Claim
40 words
A circuit as defined in claim 5 including means for setting and clearing higher order bits in the counter during testing of the logic circuit and prior to reaching a clock count to those higher order bits by the counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |