US5672525A
Expired / Lapsed
US
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Polysilicon gate reoxidation in a gas mixture of oxygen and nitrogen trifluoride gas by rapid thermal processing to improve hot carrier immunity
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1996-05-23
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Granted: 1997-09-30
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Expires: 2016-05-23
Abstract
Abstract A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Inventors
- 👤 Yang Pan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/01342; H10D64/01346; H10D64/021; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/683
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
108 words
A method of forming an FET transistor comprising the steps as follows: Forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein, forming a silicon oxide layer over said stack of said gate oxide layer and said control gate electrode and exposed portions of said semiconductor substrate including said source/drain regions, fluorinating said silicon oxide layer and the corners of said gate oxide layer by rapid thermal processing providing a fluorinated silicon oxide layer, wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas.
Claim 2
Independent Claim
108 words
A method of forming an FET transistor comprising the steps as follows: Forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein, forming a silicon oxide layer over said stack of said gate oxide layer and said control gate electrode and exposed portions of said semiconductor substrate including said source/drain regions, fluorinating said silicon oxide layer and the corners of said gate oxide layer by rapid thermal processing providing a fluorinated silicon oxide layer, wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas.
Claim 3
Dependent Claim
25 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed at a temperature from about 900° C. to about 1050° C.
Claim 4
Dependent Claim
37 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds.
Claim 5
Dependent Claim
36 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C.
Claim 6
Dependent Claim
48 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds.
Claim 7
Dependent Claim
42 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 8
Dependent Claim
42 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed at a temperature from about 900° C. to about 1050° C. and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 9
Dependent Claim
54 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 10
Dependent Claim
53 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C. and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 11
Dependent Claim
65 words
A method in accordance with claim 1 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds, and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 12
Dependent Claim
26 words
A method in accordance with claim 1 wherein the control gate electrode comprises a polycide structure comprising a layer of polysilicon and a tungsten silicide layer.
Claim 13
Independent Claim
124 words
A method of forming an FET transistor comprising the steps as follows: Forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein, forming a silicon oxide layer over said stack of said gate oxide layer and said control gate electrode and over exposed portions of said semiconductor substrate including said source/drain regions, said silicon oxide layer having a thickness from about 200 Å to about 400 Å, fluorinating said silicon oxide layer and the corners of said gate oxide layer by rapid thermal processing providing a fluorinated silicon oxide layer, wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas.
Claim 14
Independent Claim
124 words
A method of forming an FET transistor comprising the steps as follows: Forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein, forming a silicon oxide layer over said stack of said gate oxide layer and said control gate electrode and over exposed portions of said semiconductor substrate including said source/drain regions, said silicon oxide layer having a thickness from about 200 Å to about 400 Å, fluorinating said silicon oxide layer and the corners of said gate oxide layer by rapid thermal processing providing a fluorinated silicon oxide layer, wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas.
Claim 15
Dependent Claim
65 words
A method in accordance with claim 12 wherein said rapid thermal processing is performed in an atmosphere of NF 3 gas and O 2 gas at a temperature from about 900° C. to about 1050° C. for a time duration from about 10 seconds to about 50 seconds, and said fluorinated silicon oxide layer has a thickness from about 200 Å to about 400 Å.
Claim 16
Dependent Claim
26 words
A method in accordance with claim 12 wherein the control gate electrode comprises a polycide structure comprising a layer of polysilicon and a tungsten silicide layer.
Claim 17
Dependent Claim
26 words
A method in accordance with claim 14 wherein the control gate electrode comprises a polycide structure comprising a layer of polysilicon and a tungsten silicide layer.
References Cited (Backward Citations)
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