Information processing system and information processing method for executing instructions in parallel

Claim 2

An information processing system for parallel execution of sequentially-ordered instructions, comprising: a plurality of execution units, each executing processing required by an instruction; a memory storing a series of instructions which include instructions which require different processing times than each other; an instruction fetch circuit connected to said memory, fetching instructions from said memory; an instruction decoding circuit connected to said instruction fetch circuit, decoding the instructions fetched by said instruction fetch circuit; and a set-up circuit, connected to said instruction decoding circuit and said plurality of execution units, setting-up the decoded instructions decoded by said instruction decoding circuit into the execution units in such a manner that a group of decoded instructions which are to be executed next and which may require processing times different than each other are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions which have previously been set-up by the set-up circuit, and which may require processing times different than each other; wherein said set-up circuit includes means for selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been decoded already but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order.

Claim 3

An information processing system according to claim 1, further comprising: an instruction fetch circuit, simultaneously fetching a plurality of instructions from said memory to said instruction decoding circuit; wherein said instruction decoding circuit includes a plurality of instruction decoders, each decoding one of the simultaneously fetched plurality of instructions simultaneously with each other.

Claim 4

An information processing system according to claim 2, wherein a maximum number of the decoded instructions simultaneously set-up by said set-up circuit is different from a total number of instructions decoded simultaneously by said instruction decoders.

Claim 5

An information processing system according to claim 3, wherein said maximum number is larger than said total number.

Claim 6

An information processing system according to claim 1, wherein said means for selecting included in said set-up circuit selects as the group of decoded instructions to be executed next, a variable number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have already been decoded but have not yet been set-up, under said condition.

Claim 7

An information processing system according to claim 1, wherein said set-up circuit includes: a detect circuit detecting whether execution time for processing each of a predetermined number of sequentially ordered decoded instructions is not greater than an execution time for processing required by a succeeding instruction within the predetermined number of decoded instructions; and a select circuit connected to said detect circuit and responsive to a result of detection thereby for selecting, as the group of decoded instructions to be executed next, a variable number of decoded instructions from the predetermined number of decoded instructions, wherein the variable number of decoded instructions are ordered sequentially and next in order after the preceding group of decoded instructions and satisfy a condition that within the variable number of decoded instructions no instruction has a longer required processing time than any of the variable number of decoded instructions which succeed it in the sequential order.

Claim 8

An information processing system according to claim 1, wherein said set-up circuit includes means for selecting, as the group of decoded instructions to be executed next, a variable number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions from among the decoded instructions which have been decoded by said instruction decoding circuit but have not been set-up into said plurality of execution units, under a first condition that the plurality of execution units includes execution units respectively required by the variable number of decoded instructions and under a second condition that within the number of decoded instructions no instruction has a longer required processing time than any of the instructions of the number of decoded instructions which succeeds it in the sequential order.

Claim 9

An information processing system according to claim 1, wherein said set-up circuit includes: a first detect circuit detecting whether the plurality of execution units includes execution units respectively required by a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, among decoded instructions which have already been decoded but have not yet been set-up; a second detect circuit detecting whether execution time for processing one of a predetermined number of decoded instructions ordered sequentially is not greater than an execution time for processing required by a succeeding one of the predetermined number of decoded instructions; and a select circuit, connected to said first and second detect circuits and responsive to results of detection by said first and second detect circuit, selecting, as the group of decoded instructions to be executed next, a variable number of decoded instructions from the predetermined number of decoded instructions, wherein the variable number of decoded instructions are ordered sequentially and next in order after the preceding group of decoded instructions.

Claim 10

An information processing system according to claim 1, further comprising: an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the ones of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or plural other processings required by one or plural other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 11

An information processing system according to claim 9, wherein said set-up circuit delays set-up of the group of decoded instructions succeeding said one group of decoded instructions until execution of the delayed one or plural processings is complete.

Claim 12

An information processing system according to claim 9, wherein said execution control circuit delays start of both the one processing and the one or plural other processings when a memory operand required by the one processing is not yet available for use.

Claim 13

An information processing system according to claim 9, further comprising: memory operand fetch means, connected to said instruction decode circuit, for fetching, from said memory, memory operands required by instructions decoded by said instruction decoding circuit; operand buffer, connected to said memory and said set-up circuit, holding memory operands fetched from said memory by said operand fetch means and supplying memory operands required by plural ones of the group of decoded instructions set-up by the set-up circuit for use in processings required by those plural decoded instructions, when those required memory operands have been already fetched from said memory when the group of decoded instructions have been set-up; and an operand wait control circuit, connected to said set-up circuit and said memory, supplying to said execution control circuit a signal indicative that a memory operand is not yet available for use, when a memory operand required by the one decoded instruction has not yet been fetched from said memory.

Claim 14

An information processing system according to claim 1, wherein each execution unit includes: means responsive to one of a preceding group of decoded instructions which has been set-up into said execution unit for providing result data as a result of execution of processing requested by said one decoded instruction; and means for generating an end-of-processing signal indicative of completion of execution of the processing in synchronism with providing of the result data by said providing means; wherein said set-up circuit includes means for setting-up a group of decoded instructions to be executed next in response to receipt of end-of-processing signals from said means for generating from all of said different ones of the execution units into which said preceding group of processing have been set-up.

Claim 15

An information processing system according to claim 13, further including a plurality of registers connected to said plurality of execution units, wherein each execution unit further includes: means responsive to designation of one of the plurality of registers as a result register by one of the preceding group of decoded instructions which has been set-up into said execution unit for writing result data provided by said providing means of said execution unit into said designated register.

Claim 16

An information processing system according to claim 1, wherein said set-up circuit includes means for selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been decoded but have not yet been set up under said condition; and means for setting-up a starting one of the decoded instructions which have already been decoded but have not yet been set-up, into one of said execution units in case no such number of decoded instructions satisfy said condition.

Claim 17

An information processing system according to claim 1, wherein said set-up circuit includes: a detect circuit detecting whether execution time for processing each of a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, is not greater than an execution time for processing required by a succeeding instruction within the predetermined number of decoded instructions; a select circuit connected to said detect circuit and responsive to a result of detection thereby for selecting the predetermined number of decoded instructions, as the group of decoded instructions to be executed next, in case the predetermined number of decoded instructions satisfy said condition; and means for setting-up a starting one of the predetermined number of decoded instructions into one of said execution units, in case the predetermined number of decoded instructions do not satisfy said condition.

Claim 18

An information processing system according to claim 1, wherein said set-up circuit includes: means for selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions from among decoded instructions which have been decoded by said instruction decoding circuit but have not yet been set-up, under a first condition that the plurality of execution units includes execution units respectively required by the number of decoded instructions and under a second condition that within the number of decoded instructions no instruction has a longer required processing time than any of the instructions of the number of decoded instructions which succeeds it in the sequential order; and means for setting up a starting one of the number of decoded instructions next in order to said preceding group of decoded instructions, into one of said execution units, in case the number of decoded instructions do not satisfy the first and second conditions.

Claim 19

An information processing system according to claim 1, wherein said set-up circuit includes: a first detect circuit detecting whether the plurality of execution units includes execution units respectively required by a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, among decoded instructions which have been decoded already but have not yet been set-up; a second detect circuit detecting whether execution time for processing each of a predetermined number of decoded instructions ordered sequentially is not greater than an execution time for processing required by a succeeding one of the predetermined number of decoded instructions; and a select circuit, connected to said first and second detect circuits and responsive to results of detection by said first and second detect circuit, selecting the predetermined number of decoded instructions, as the group of decoded instructions to be executed next, in case the predetermined number of decoded instructions satisfy said condition; and means for setting-up a starting one of the predetermined number of decoded instructions into one of the execution units, in case the predetermined number of decoded instructions do not satisfy said condition.

Claim 20

An information processing system according to claim 18, further comprising: an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 21

An information processing system according to claim 19, wherein said set-up circuit delays set-up of the group of decoded instructions held in said instruction decoding circuit succeeding to said one group of decoded instructions until execution of the delayed one or more processings is complete.

Claim 22

An information processing system according to claim 19, wherein said execution control circuit delays start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 23

An information processing system according to claim 19, further comprising: memory operand fetch means, connected to said instruction decoding circuit, for fetching, from said memory, memory operands required by instructions decoded by said instruction decoding circuit; an operand buffer, connected to said memory and said set-up circuit, holding memory operands fetched from said memory by said operand fetch means and supplying memory operands required by a plurality of the group of decoded instructions set-up by the set-up circuit for use in processings required by those decoded instructions, when those required memory operands have already been fetched from said memory when the group of decoded instructions have been set-up; and an operand wait control circuit, connected to said set-up circuit and said memory, supplying to said execution control circuit a signal indicative that a memory operand is not yet available for use, when a memory operand required by the one decoded instruction has not yet been fetched from said memory.

Claim 24

An information processing system according to claim 18, further comprising an instruction queue connected to said decoding circuit and said set-up circuit for temporarily holding each of the decoded instructions decoded by said instruction decoding circuit at least until said decoded instruction is set-up by said set-up circuit.

Claim 25

An information processing system according to claim 1, further comprising an instruction queue connected to said decoding circuit and said set-up circuit for temporarily holding each of the decoded instructions decoded by said instruction decoding circuit at least until said decoded instruction is set-up by said set-up circuit.

Claim 26

An information processing system for parallel execution of sequentially-ordered instructions, comprising: a plurality of execution units, each execution unit executing processing required by an instruction; a memory storing a series of instructions; an instruction fetch circuit connected to said memory, fetching instructions from said memory; an instruction decoding circuit connected to said instruction fetch circuit decoding the instructions fetched by said instruction fetch circuit; a set-up circuit, connected to said instruction decoding circuit and said plurality of execution units, setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the set-up circuit; and an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 27

An information processing system for parallel execution of sequentially-ordered instructions, comprising: a plurality of execution units, each execution unit executing processing required by an instruction; a memory storing a series of instructions; an instruction fetch circuit connected to said memory, fetching instructions from said memory; an instruction decoding circuit connected to said instruction fetch circuit decoding the instructions fetched by said instruction fetch circuit; a set-up circuit, connected to said instruction decoding circuit and said plurality of execution units, setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the set-up circuit; and an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 28

An information processing system according to claim 25, wherein said execution control circuit delays start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 29

An information processing system according to claim 25, further comprising an instruction queue connected to said decoding circuit and said set-up circuit for temporarily holding each of the decoded instructions decoded by said instruction decoding circuit at least until said decoded instruction is set-up by said set-up circuit.

Claim 30

An information processing system for parallel execution of sequentially-ordered instructions, comprising: a plurality of execution units, each execution unit executing processing required by an instruction; a memory storing a series of instructions; an instruction fetch circuit connected to said memory, fetching instructions from said memory: an instruction decoding circuit connected to said instruction fetch circuit decoding the instructions fetched by said instruction fetch circuit; a set-up circuit, connected to said instruction decoding circuit and said plurality of execution units, setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the set-up circuit; wherein said set-up circuit includes means for selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been already decoded but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order; and said information processing system further comprising: an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 31

An information processing system for parallel execution of sequentially-ordered instructions, comprising: a plurality of execution units, each execution unit executing processing required by an instruction; a memory storing a series of instructions; an instruction fetch circuit connected to said memory, fetching instructions from said memory: an instruction decoding circuit connected to said instruction fetch circuit decoding the instructions fetched by said instruction fetch circuit; a set-up circuit, connected to said instruction decoding circuit and said plurality of execution units, setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the set-up circuit; wherein said set-up circuit includes means for selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been already decoded but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order; and said information processing system further comprising: an execution control circuit connected to said set-up circuit and said plurality of execution units, controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding to the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 32

An information processing system according to claim 28, wherein said execution control circuit delays the start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 33

An information processing system according to claim 28, further comprising an instruction queue connected to said decoding circuit and said set-up circuit for temporarily holding each of the decoded instructions decoded by said instruction decoding circuit at least until said decoded instruction is set-up by said set-up circuit.

Claim 34

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing in a memory a series of said plurality of instructions which include instructions which require different processing times than each other; fetching instructions from said memory; decoding the fetched instructions; setting-up the decoded instructions into the execution units in such a manner that a group of decoded instructions which are to be executed next and which may require processing times different than each other are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions which have previously been setup, and which may require processing times different than each other; selecting as the group of decoded instructions to be executed next a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been decoded already but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order.

Claim 35

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing in a memory a series of said plurality of instructions which include instructions which require different processing times than each other; fetching instructions from said memory; decoding the fetched instructions; setting-up the decoded instructions into the execution units in such a manner that a group of decoded instructions which are to be executed next and which may require processing times different than each other are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions which have previously been setup, and which may require processing times different than each other; selecting as the group of decoded instructions to be executed next a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been decoded already but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order.

Claim 36

An information processing method according to claim 31, wherein said fetching step comprises simultaneously fetching a plurality of instructions from said memory and wherein said decoding step simultaneously decodes the simultaneously fetched plurality of instructions.

Claim 37

An information processing method according to claim 32, wherein a maximum number of the decoded instructions simultaneously set-up in said setting-up step is different from a total number of instructions simultaneously decoded in said decoding step.

Claim 38

An information processing method according to claim 33, wherein said maximum number is larger than said total number.

Claim 39

An information processing method according to claim 31, wherein said selecting step selects as the group of decoded instructions to be executed next, a variable number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have already been decoded but have not yet been set-up, under said condition.

Claim 40

An information processing method according to claim 31, further comprising steps of: detecting whether execution time for processing each of a predetermined number of sequentially ordered decoded instructions is not greater than an execution processing required by a succeeding instruction within the predetermined number of decoded instructions; and in response to a result of said detecting step, selecting as the group of decoded instructions to be executed next, a variable number of decoded instructions from the predetermined number of decoded instructions, wherein the variable number of decoded instructions are ordered sequentially and next in order after the preceding group of decoded instructions and satisfy a condition that within the variable number of decoded instructions no instruction has a longer required processing time than any of the variable number of decoded instructions which succeed it in the sequential order.

Claim 41

An information processing method according to claim 31, wherein said selecting step further comprises selecting, as the group of decoded instructions to be executed next, a variable number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions from among the decoded instructions which have been decoded by said instruction decoding step but have not been set-up into said plurality of execution units, under a first condition that the plurality of execution units includes execution units respectively required by the variable number of decoded instructions and under a second condition that within the number of decoded instructions no instruction has a longer required processing time than any of the instructions of the number of decoded instructions which succeeds it in the sequential order.

Claim 42

An information processing method according to claim 31, further comprising steps of: detecting whether the plurality of execution units includes execution units respectively required by a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, among decoded instructions which have already been decoded but have not yet been set-up; detecting whether execution time for processing one of a predetermined number of decoded instructions ordered sequentially is not greater than an execution time for processing required by a succeeding one of the predetermined number of decoded instructions; and in response to results of said detecting steps, selecting, as the group of decoded instructions to be executed next, a variable number of decoded instructions from the predetermined number of decoded instructions, wherein the variable number of decoded instructions are ordered sequentially and next in order after the preceding group of decoded instructions.

Claim 43

An information processing method according to claim 31, further comprising a step of controlling initiation of execution of processing by each of the ones of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or plural other processings required by one or plural other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 44

An information processing method according to claim 39, further comprising a step of delaying set-up of the group of decoded instructions succeeding said one group of decoded instructions until execution of the delayed one or plural processings is complete.

Claim 45

An information processing method according to claim 39, further comprising a step of delaying start of both the one processing and the one or plural other processings when a memory operand required by the one processing is not yet available for use.

Claim 46

An information processing method according to claim 39, further comprising steps of: fetching, from said memory, memory operands required by instructions decoded by said instruction decoding circuit; holding in a buffer memory operands fetched from said memory; supply memory operands required by plural ones of the group of decoded instructions set-up by the setting-up step for use in processings required by those plural decoded instructions when those required memory operands have already been fetched from said memory when the group of decoded instructions have been set-up; and supplying to said controlling step a signal indicative that a memory operand is not yet available for use, when a memory operand required by the one decoded instruction has not yet been fetched from said memory.

Claim 47

An information processing method according to claim 31, further comprising steps of: in response to one of a preceding group of decoded instructions which has been set-up into said execution unit, providing result data as a result of execution of processing requested by said one decoded instruction; generating an end-of-processing signal indicative of completion of execution of the processing in synchronism with providing of the result data by said providing step; and setting-up a group of decoded instructions to be executed next in response to receipt of end-of-processing signals from said generating step from all of said different ones of the execution units into which said preceding group of processing have been set-up.

Claim 48

An information processing method according to claim 43, wherein a plurality of registers are connected to said plurality of execution units, further comprising steps of: designating one of the plurality of registers as a result register by one of the preceding group of decoded instructions which has been set-up into said execution unit; and writing result data provided by said providing step into said designated register.

Claim 49

An information processing method according to claim 31, further comprising steps of: selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been decoded but have not yet been set up under said condition; and setting-up a starting one of the decoded instructions which have already been decoded but have not yet been set-up, into one of said execution units in case no such number of decoded instructions satisfy said condition.

Claim 50

An information processing method according to claim 31, further comprising steps of: detecting whether execution time for processing each of a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, is not greater than an execution time for processing required by a succeeding instruction within the predetermined number of decoded instructions; in response to a result of said detecting step, selecting the predetermined number of decoded instructions, as the group of decoded instructions to be executed next, in case the predetermined number of decoded instructions satisfy said condition; and setting-up a starting one of the predetermined number of decoded instructions into one of said execution units, in case the predetermined number of decoded instructions do not satisfy said condition.

Claim 51

An information processing method according to claim 31, further comprising steps of: selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions from among decoded instructions which have been decoded by said decoding step but have not yet been set-up, under a first condition that the plurality of execution units includes execution units respectively required by the number of decoded instructions and under a second condition that within the number of decoded instructions no instruction has a longer required processing time than any of the instructions of the number of decoded instructions which succeeds it in the sequential order; and setting-up a starting one of the number of decoded instructions next in order to said preceding group of decoded instructions into one of said execution units, in case the number of decoded instructions do not satisfy the first and second conditions.

Claim 52

An information processing method according to claim 31, further comprising steps of: detecting whether the plurality of execution units includes execution units respectively required by a predetermined number of decoded instructions ordered sequentially and next in order after the preceding group of decoded instructions, among decoded instructions which have been decoded already but have not yet been set-up; detecting whether execution time for processing each of a predetermined number of decoded instructions ordered sequentially is not greater than an execution time for processing required by a succeeding one of the predetermined number of decoded instructions; in response to results of said detecting steps, selecting the predetermined number of decoded instructions, as the group of decoded instructions to be executed next, in case the predetermined number of decoded instructions satisfy said condition; and setting-up a starting one of the predetermined number of decoded instructions into one of the execution units in case the predetermined number of decoded instructions do not satisfy said condition.

Claim 53

An information processing method system according to claim 48, further comprising a step of controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 54

An information processing method according to claim 49, further comprising a step of delaying set-up of the group of decoded instructions decoded in said instruction decoding step succeeding said one group of decoded instructions until execution of the delayed one or more processings is complete.

Claim 55

An information processing method according to claim 49, further comprising a step of delaying start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 56

An information processing method according to claim 49, further comprising steps of: fetching, from said memory, memory operands required by instructions decoded by said instruction decoding step; holding in a buffer memory operands fetched from said memory by said fetching step; supplying memory operands required by a plurality of the group of decoded set-up instructions for use in processings required by those decoded instructions, when those required memory operands have already been fetched from said memory when the group of decoded instructions have been set-up; and supplying to said controlling step a signal indicative that a memory operand is not yet available for use, when a memory operand required by the one decoded instruction has not yet been fetched from said memory.

Claim 57

An information processing method according to claim 48, further comprising a step of temporarily holding each of the decoded instructions decoded by said decoding step at least until said decoded instruction is set-up by said setting-up step.

Claim 58

An information processing method according to claim 31, further comprising a step of temporarily holding each of the decoded instructions decoded by said decoding step at least until said decoded instruction is set-up by said setting-up step.

Claim 59

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing a series of said plurality of instructions in a memory; fetching instructions from said memory; decoding the fetched instructions; setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the setting-up step; and controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 60

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing a series of said plurality of instructions in a memory; fetching instructions from said memory; decoding the fetched instructions; setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the setting-up step; and controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 61

An information processing method according to claim 55, further comprising a step of delaying a start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 62

An information processing method according to claim 55, further comprising a step of temporarily holding each of the decoded instructions decoded by said decoding step at least until said decoded instruction is set-up by said setting-up step.

Claim 63

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing a series of said plurality of instructions in a memory; fetching instructions from said memory: decoding the fetched instructions; setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the setting-up step; selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been already decoded but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order; and controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 64

An information processing method for parallel execution of a plurality of sequentially-ordered instructions, wherein a plurality of execution units each execute processing required by one of said plurality of instructions, said method comprising steps of: storing a series of said plurality of instructions in a memory; fetching instructions from said memory: decoding the fetched instructions; setting-up decoded instructions into the execution units in such a manner that a group of decoded instructions to be executed next are set-up simultaneously into different ones of said plurality of execution units, each of which is capable of executing processing required by one of the instructions of the group of decoded instructions, in response to completion of execution, by different ones of said plurality of execution units, of the processing of instructions of a preceding group of decoded instructions previously set-up by the setting-up step; selecting, as the group of decoded instructions to be executed next, a number of decoded instructions ordered sequentially and next in order to the preceding group of decoded instructions from among decoded instructions which have been already decoded but have not yet been set-up, under a condition that within the selected group no instruction has a longer required processing time than any of the instructions of the group of decoded instructions which succeed it in the sequential order; and controlling initiation of execution of processing by each of the plurality of execution units for which the group of decoded instructions have been set-up, so that a start of execution of both one processing required by one of the group of decoded instructions and one or more other processings required by one or more other decoded instructions succeeding the one decoded instruction within the groups are delayed, when the one processing needs to be delayed.

Claim 65

An information processing method according to claim 58, further comprising a step of delaying the start of both the one processing and the one or more other processings when a memory operand required by the one processing is not yet available for use.

Claim 66

An information processing method according to claim 58, further comprising a step of temporarily holding each of the decoded instructions decoded by said decoding step at least until said decoded instruction is set-up by said setting-up step.