Command word decoding unit

Abstract

Abstract PURPOSE:To redouble the processing capability of a decoding unit, by holding the head one of plural instruction words, selecting one of the plural instruction words in response to the type of the head instruction word, and then requesting the instruction address to be sent out next to a storage unit. CONSTITUTION:A signal showing that an effective instruction word data is transmitted via a signal line 109, is sent to a decoding unit 4 from a storage unit 1. The instruction word data is divided into prescribed bytes and then transmitted to data lines 101-104. The 1st instruction in the instruction word data is stored in an instruction word register 450, and the 2nd instruction is selected by selecting circuits 401 and 402 to be stored in a register 451. The signals showing the validity of the 1st and 2nd instructions, a request signal for an effective instruction word of the next cycle and a signal showing the increment value of an instruction address are sent to FF452, 453 and 431 as well as an adder 420 respectively from a logical circuit 410. The type information of each instruction and operand addresses are sent to a preparation unit 2 from logical circuits 460, 461, 470 and 471 respectively. Then a request address of an effective instruction word which is given to the unit 1 is transmitted from the FF431 and a register 430.

Inventors

• 👤 Shunichi Torii
• 👤 俊一 鳥居
• 👤 Tsuguo Shimizu
• 👤 清水　嗣雄
• 👤 Kenichi Wada
• 👤 健一 和田
• 👤 Yoichi Shintani
• 👤 洋一 新谷
• 👤 Akira Yamaoka
• 👤 山岡　彰
• 👤 Giichi Tanaka
• 👤 義一 田中

Bibliographic Details