Data processing system having pipeline arithmetic/logic units

Claim 1

A data processing system in which a plurality of element data are subject to an arithmetic or logic operation sequentially by a single instruction and operational results for sets of said element data are stored sequentially in a memory by said instruction, comprising: pipeline arithmetic and logic operation means including a plurality of stages connected in series are performing an arithmetic or logic operation specified by said instruction sequentially operating on said sets of element data while passing said sets of element data through said stages; check information means for transmitting check information indicative of the presence or absence of a fault occurring in each of said stages in synchronism with the flow of said element data in said pipeline arithmetic and logic operation means; request control means for issuing a store request to said memory each time an operational result of each set of element data is obtained while passing through said stages for sequentially storing said operational results of said respective sets of element data in said memory in response to a signal from said pipeline arithmetic and logic operation means; and counter means for counting the number of store requests issued by said request control means, said request control means including first suppressing means for suppressing the issuance of said store request in response to said check information being indicative of a fault in said operational result which is being stored in said memory.