Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
143 words
Apparatus for supplying, in response to user commands, independent streams of output data to a plurality of users, comprising: a parallel processing computer containing a plurality of processors each connected to an information storage device; an input/output circuit, connected to each of said processors, for distributing an input data stream amongst the processors such that each of the information storage devices stores a portion of the input data stream; interface means, connected between said parallel processing computer and said users, for interpreting said user commands and causing said parallel processing computer to access, from each of said information storage devices, stored input data in accordance with the user commands; and enabling each individual user to manipulate the stream of data supplied to that individual user said input/output circuit supplies each of said users with said accessed data as a stream of output data.
Claim 2
Dependent Claim
143 words
Apparatus for supplying, in response to user commands, independent streams of output data to a plurality of users, comprising: a parallel processing computer containing a plurality of processors each connected to an information storage device; an input/output circuit, connected to each of said processors, for distributing an input data stream amongst the processors such that each of the information storage devices stores a portion of the input data stream; interface means, connected between said parallel processing computer and said users, for interpreting said user commands and causing said parallel processing computer to access, from each of said information storage devices, stored input data in accordance with the user commands; and enabling each individual user to manipulate the stream of data supplied to that individual user said input/output circuit supplies each of said users with said accessed data as a stream of output data.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1 wherein said manipulations include starting, stopping, pausing, fast-forwarding, and fast-reversing the stream of data.
Claim 4
Dependent Claim
15 words
The apparatus of claim 1 wherein said stream of input data is a multimedia program.
Claim 5
Dependent Claim
13 words
The apparatus of claim 1 wherein said information storage devices are disk drives.
Claim 6
Dependent Claim
40 words
The apparatus of claim 1 wherein said input/output circuit further comprises a multiplexing circuit such that multiple streams of output data are multiplexed with one another upon a transmission means for carrying said streams of output data to said users.
Claim 7
Dependent Claim
22 words
The apparatus of claim 1 further comprising a mass storage device for supplying said input/output circuit with said stream of input data.
Claim 8
Dependent Claim
34 words
The apparatus of claim 1 wherein said input/output circuit further comprises an interprocessor communications bus for enabling each of said processors to communicate with each of said other processors within said parallel processing computer.
Claim 9
Dependent Claim
27 words
The apparatus of claim 1 wherein said input/output circuit further comprises a output timing sequencer that reorders segments of data that comprise said stream of output data.
Claim 10
Dependent Claim
138 words
The apparatus of claim 8 wherein said output timing sequencer further comprises: a register array for storing each of said data segments and a data segment identifying value for each of the data segments such that each data segment can be addressed by said segment identifying value; a counter, connected to said register array, for incrementally counting such that each count of said counter corresponds to one segment identifying value in a series of segment identifying values; means, connected to said register array and said counter, for retrieving a data segment corresponding to said segment identifying value generated by the counter; and means for repeating said retrieval of said data segments for each count of said counter such that an order of said data segments is consistent with an order in which the counter produces segment identifying values.
Claim 11
Dependent Claim
32 words
The apparatus of claim 1 further comprising means for storing additional input data in said information storage devices without interrupting production of said stream of output data for each of said users.
Claim 12
Dependent Claim
33 words
The apparatus of claim 1 further comprising means for identifying and correcting errors in said stream of output data without interrupting production of said stream of output data for each of said users.
Claim 13
Dependent Claim
68 words
The apparatus of claim 1 further comprising means for placing one or more of the information storage devices in an idle mode where data access is not being conducted to or from the information storage device, such that the information storage device is implicitly or explicitly triggered to perform internal housekeeping or recalibration tasks, without interrupting production of said stream of output data for each of said users.
Claim 14
Dependent Claim
35 words
The apparatus of claim 1 further comprising means for allocating users to the plurality of processors such that each user can utilize at least one processor to access data within an associated information storage device.
Claim 15
Dependent Claim
141 words
Apparatus for reordering data segments in a continuous stream of data segments, said apparatus comprising: a register array for storing each of said data segments and a data segment identifying value for each of the data segments such that each data segment can be addressed by said segment identifying value; a counter, connected to said register array, for incrementally counting such that each count of said counter corresponds to one segment identifying value in a series of segment identifying values; means, connected to said register array and said counter, for retrieving a data segment corresponding to said segment identifying value generated by the counter; and means for repeating said retrieval of said data segments for each count of said counter such that an order of said data segments is consistent with an order in which the counter produces segment identifying values.
Claim 16
Dependent Claim
141 words
Apparatus for reordering data segments in a continuous stream of data segments, said apparatus comprising: a register array for storing each of said data segments and a data segment identifying value for each of the data segments such that each data segment can be addressed by said segment identifying value; a counter, connected to said register array, for incrementally counting such that each count of said counter corresponds to one segment identifying value in a series of segment identifying values; means, connected to said register array and said counter, for retrieving a data segment corresponding to said segment identifying value generated by the counter; and means for repeating said retrieval of said data segments for each count of said counter such that an order of said data segments is consistent with an order in which the counter produces segment identifying values.
Claim 17
Dependent Claim
75 words
The apparatus of claim 14 further comprising: a plurality of register arrays, each connected to independent streams of data segments and each data segment is associated with a unique segment identifying value; said counter is connected to each of said register arrays; and means, connected to said counter and said register arrays, for retrieving from one of the plurality of register arrays a data segment corresponding to a segment identifying value generated by said counter.
Claim 18
Dependent Claim
41 words
The apparatus of claim 15 wherein said independent streams of data segments are generated by a parallel processing computer containing a plurality of parallel processors such that each data segment is produced by one processor in said plurality of parallel processors.
Claim 19
Dependent Claim
26 words
The apparatus of claim 15 wherein said plurality of register arrays are a plurality of output registers of said processors in said plurality of parallel processors.