Patent US5668766A successfully refreshed from Google Patents.
US5668766A
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Method and apparatus for increasing memory read access speed using double-sensing
Assignee: Intel Corp
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Filing: 1996-05-16
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Granted: 1997-09-16
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Expires: 2016-05-16
Abstract
Abstract Double-sensing of a data store being read to increase overall memory read access speed. An indicator signal coupled to the data store being read is responsive to a value stored in the data store. A first sense amplifier has a first input coupled to the indicator signal, a second input coupled to receive a first sense enable signal at a first sense time and an output coupled to provide a first indicated data value responsive to the first sense enable signal and the indicator signal. A second sense amplifier has a first input coupled to the indicator signal, a second input coupled to receive a second sense enable signal at a second sense time, and an output coupled to provide a second indicated data value responsive to the second sense enable signal and the indicator signal. In one embodiment, a first input of a comparator is coupled to the output of the first sense amplifier and a second input of the comparator is coupled to the output of the second sense amplifier. An output of the comparator is coupled to a signal which invalidates the first indicated value if the first indicated value sensed at the first sense time is different than the second indicated value sensed at the second sense time.
Inventors
- 👤 Arkady Bramnik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:24
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
184 words
An apparatus for reading a value stored in a memory cell in a computer system, the apparatus comprising: a first sense amplifier coupled to the memory cell, the first sense amplifier having an input coupled to receive a first sense enable signal at a first sense time, and an output coupled to provide to a data bus a first indicated data value responsive to the first sense enable signal, the data bus being coupled to a processor such that the first indicated value is provided to the processor at the first sense time; a second sense amplifier coupled to the memory cell, the second sense amplifier having an input coupled to receive a second sense enable signal at a second, later sense time, and an output coupled to provide a second indicated data value responsive to the second sense enable signal; and a comparator coupled to the first and second sense amplifiers, the comparator issuing a signal to invalidate the first indicated data value and providing the second indicated data value to the processor if the first and second indicated data values are different.
Claim 2
Independent Claim
184 words
An apparatus for reading a value stored in a memory cell in a computer system, the apparatus comprising: a first sense amplifier coupled to the memory cell, the first sense amplifier having an input coupled to receive a first sense enable signal at a first sense time, and an output coupled to provide to a data bus a first indicated data value responsive to the first sense enable signal, the data bus being coupled to a processor such that the first indicated value is provided to the processor at the first sense time; a second sense amplifier coupled to the memory cell, the second sense amplifier having an input coupled to receive a second sense enable signal at a second, later sense time, and an output coupled to provide a second indicated data value responsive to the second sense enable signal; and a comparator coupled to the first and second sense amplifiers, the comparator issuing a signal to invalidate the first indicated data value and providing the second indicated data value to the processor if the first and second indicated data values are different.
Claim 3
Dependent Claim
16 words
The apparatus as set forth in claim 1 wherein the memory is a cache memory cell.
Claim 4
Dependent Claim
16 words
The apparatus as set forth in claim 1 wherein the memory is a flash memory cell.
Claim 5
Dependent Claim
19 words
The apparatus as set forth in claim 1 wherein the first and second sense amplifiers are bistable sense amplifiers.
Claim 6
Dependent Claim
165 words
A computer system comprising: a bus to communicate information a processor coupled to the bus to process information; and a cache memory coupled to the processor to store information, the cache memory including: an array of memory cells including a first memory cell to be read, a first sense amplifier coupled to the first memory cell and having an output coupled to an input of the processor, the first sense amplifier providing a first indicated data value to the processor at a first sense time, a second sense amplifier coupled to the first memory cell, the second sense amplifier providing a second indicated data value on an output at a second, later sense time, and a comparator having inputs coupled to the first and second sense amplifier and an output coupled to the processor, the comparator invalidating the first indicated data value provided to the processor and providing the second indicated data value to the processor if the first and second data values are different.
Claim 7
Dependent Claim
165 words
A computer system comprising: a bus to communicate information a processor coupled to the bus to process information; and a cache memory coupled to the processor to store information, the cache memory including: an array of memory cells including a first memory cell to be read, a first sense amplifier coupled to the first memory cell and having an output coupled to an input of the processor, the first sense amplifier providing a first indicated data value to the processor at a first sense time, a second sense amplifier coupled to the first memory cell, the second sense amplifier providing a second indicated data value on an output at a second, later sense time, and a comparator having inputs coupled to the first and second sense amplifier and an output coupled to the processor, the comparator invalidating the first indicated data value provided to the processor and providing the second indicated data value to the processor if the first and second data values are different.
Claim 8
Dependent Claim
19 words
The computer system as set forth in claim 5 wherein the cache memory is a set associative cache memory.
Claim 9
Dependent Claim
35 words
The computer system as set forth in claim 6 wherein the comparator further indicates that a way of the set associative cache memory is not matched if the first and second data values are different.
Claim 10
Dependent Claim
20 words
The computer system as set forth in claim 5 wherein the first and second sense amplifiers are bistable sense amplifiers.
Claim 11
Dependent Claim
18 words
The computer system as set forth in claim 5 wherein the cache memory is a cache tag memory.
Claim 12
Dependent Claim
134 words
In a computer system, a method for reading data from a memory cell comprising the steps of: accessing the memory cell for reading in response to a read request from a processor; sensing a value stored in the cell at a first time; communicating the value sensed at the first time to the processor; sensing the value stored in the cell at a second, later time; comparing the value sensed at the first time to the value sensed at the second, later time; and if the valued sensed at the first time and the value sensed at the second, later time are different, performing the steps of: sending a signal to the processor to invalidate the value sensed at the first time, and communicating the value sensed at the second time to the processor.
Claim 13
Dependent Claim
134 words
In a computer system, a method for reading data from a memory cell comprising the steps of: accessing the memory cell for reading in response to a read request from a processor; sensing a value stored in the cell at a first time; communicating the value sensed at the first time to the processor; sensing the value stored in the cell at a second, later time; comparing the value sensed at the first time to the value sensed at the second, later time; and if the valued sensed at the first time and the value sensed at the second, later time are different, performing the steps of: sending a signal to the processor to invalidate the value sensed at the first time, and communicating the value sensed at the second time to the processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |