Patent US5668484A successfully refreshed from Google Patents.
US5668484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency clock signal distribution circuit with reduced clock skew
Assignee: NEC Corp
•
Filing: 1994-09-16
•
Granted: 1997-09-16
•
Expires: 2014-09-16
Abstract
Abstract A clock signal distribution circuit of a tree structure having a plurality of buffers arranged in a plurality of hierarchical stages includes short-circuit wirings for short-circuiting output terminals of the buffers at each stage of the plurality of hierarchical stages. Each of the plurality of buffers is formed by a single inverter or a multi-stage inverter wherein an input stage inverter and an output stage inverter are connected in series. The output stage inverter has a size larger than that of the input stage inverter. The clock signal distribution circuit thus constructed can reduce clock skew and distribute a high frequency clock signal having sharp rise and fall characteristics to a plurality of registers.
Inventors
- 👤 Masahiro Nomura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:47
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
48 words
A clock signal distribution circuit having an H-tree structure, said distribution circuit comprising: a plurality of buffers arranged in a plurality of hierarchical stages, in an H-tree structure; and short-circuit wirings for short circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages.
Claim 2
Dependent Claim
48 words
A clock signal distribution circuit having an H-tree structure, said distribution circuit comprising: a plurality of buffers arranged in a plurality of hierarchical stages, in an H-tree structure; and short-circuit wirings for short circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages.
Claim 3
Dependent Claim
24 words
The clock signal distribution circuit of a tree structure according to claim 1, wherein each of said plurality of buffers comprises a single inverter.
Claim 4
Dependent Claim
41 words
The clock signal distribution circuit of a tree structure according to claim 2, wherein said single inverter includes a P-channel MOS field effect transistor and an N-channel MOS field effect transistor connected in series between a power supply source and ground.
Claim 5
Dependent Claim
126 words
A clock signal distribution circuit having an H-tree structure wherein a plurality of buffers are arranged in a plurality of hierarchical stages with the same load and the same wiring length, said clock signal distribution circuit comprising: a combination of an input stage inverter and an output stage inverter comprising each of said plurality of buffers, said output stage inverter being connected in series to said input stage inverter and formed by a transistor larger in size than that of said input stage inverter so that each of said plurality of buffers has a low output on-resistance and a small input capacitance; and a short-circuit wiring for short-circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages in said H-tree structure.
Claim 6
Dependent Claim
126 words
A clock signal distribution circuit having an H-tree structure wherein a plurality of buffers are arranged in a plurality of hierarchical stages with the same load and the same wiring length, said clock signal distribution circuit comprising: a combination of an input stage inverter and an output stage inverter comprising each of said plurality of buffers, said output stage inverter being connected in series to said input stage inverter and formed by a transistor larger in size than that of said input stage inverter so that each of said plurality of buffers has a low output on-resistance and a small input capacitance; and a short-circuit wiring for short-circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages in said H-tree structure.
Claim 7
Dependent Claim
66 words
The clock signal distribution circuit of a tree structure according to claim 4, wherein each of said input and output stage inverters are formed by a pair of opposite mode MOS field effect transistors, each of said MOS field effect transistors of said output stage inverter having a channel width larger than that of each of said MOS field effect transistors of said input stage inverter.
Claim 8
Dependent Claim
101 words
A clock signal distribution circuit of a tree structure, having a plurality of hierarchical stages, each of said hierarchical stages comprising: n buffers, where n is an integer from 1 to N, each of said n buffers comprising: at least one inverter; an input stage for supplying a clock signal to said at least one inverter; an output stage, for outputting the clock signal from said at least one inverter, said output stage connected in series to an input stage of a next one of said hierarchical stages; and a short circuit wire connecting said output stage at each hierarchical level.
Claim 9
Dependent Claim
101 words
A clock signal distribution circuit of a tree structure, having a plurality of hierarchical stages, each of said hierarchical stages comprising: n buffers, where n is an integer from 1 to N, each of said n buffers comprising: at least one inverter; an input stage for supplying a clock signal to said at least one inverter; an output stage, for outputting the clock signal from said at least one inverter, said output stage connected in series to an input stage of a next one of said hierarchical stages; and a short circuit wire connecting said output stage at each hierarchical level.
Claim 10
Dependent Claim
51 words
A clock signal distribution circuit having a tree structure as recited in claim 6, wherein each of said n buffers in each of said plurality of hierarchical stages comprises an input stage inverter and an output stage inverter, said output stage inverter being larger in size than said input stage inverter.
Claim 11
Dependent Claim
31 words
A clock signal distribution circuit having a tree structure as recited in claim 6, wherein said at least one inverter comprises a PMOS transistor connected in series with an NMOS transistor.
Claim 12
Dependent Claim
116 words
A reduced skew H-tree clock signal distribution circuit having a plurality of hierarchical stages, comprising: a first stage comprising a buffer, said buffer comprising an input for receiving a clock signal and an output for outputting the clock signal; wiring connected to said output of said first stage, said wiring arranged in an H-tree pattern having four connection points; a second stage, connected to one of said four connection points, said second stage comprising four buffers each comprising and input stage for receiving the clock signal from said first stage, and an output for outputting the clock signal; and a short-circuit wire electrically connecting together the output of each of said buffers of said second stage.
Claim 13
Dependent Claim
116 words
A reduced skew H-tree clock signal distribution circuit having a plurality of hierarchical stages, comprising: a first stage comprising a buffer, said buffer comprising an input for receiving a clock signal and an output for outputting the clock signal; wiring connected to said output of said first stage, said wiring arranged in an H-tree pattern having four connection points; a second stage, connected to one of said four connection points, said second stage comprising four buffers each comprising and input stage for receiving the clock signal from said first stage, and an output for outputting the clock signal; and a short-circuit wire electrically connecting together the output of each of said buffers of said second stage.
Claim 14
Dependent Claim
53 words
A reduced skew H-tree clock signal distribution circuit as recited in claim 9 wherein said buffers comprise: first and second inverters connected in series, said first inverter for receiving the clock signal at an input and said second inverter for outputting the clock signal said second inverter being larger than said first inverter.
Claim 15
Dependent Claim
32 words
A reduced skew H-tree clock signal distribution circuit as recited in claim 10 wherein said first and said second inverters each comprise a PMOS transistor connected in series with an NMOS transistor.
References Cited (Backward Citations)
US4661721A
Cited
JPS6313517A
Cited
US4812684A
Cited
US4833677A
Cited
EP0335697A2
Cited
EP0451079A2
Cited
US5109168A
Cited
US5410491A
Cited
JPH04373160A
Cited
US5270592A
Cited
US5396129A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |