Reducing clock skew in large-scale integrated circuits

Claim 1

A method for reducing clock skew in a digital system having a plurality of integrated-circuit chips each containing a set of functional logic circuits and each receiving the same plurality of clock signals, comprising the steps of: a) defining a plurality of clock trees for said chips and said clock signals, each of said trees having the same number of levels, said levels including one or more upper levels, an initial one of said upper levels receiving said clock signal, and including one or more deep levels, a final one of said deep levels being coupled directly to said functional logic for distributing said clock signal thereto, and defining separate fixed level delays for each level, said level delays at each of said levels being the same for all of said trees on all of said chips; b) creating clock logic for all of said trees and nets for interconnecting said logic, such that said upper levels of all said trees contain driver circuits having the same, fixed performance for each of said upper levels and also contain terminator circuits having multiple capacitances, and such that said deep levels contain driver circuits having multiple performances, potentially different for every net in said deep levels; c) for each net in each of said deep levels of all said trees, 1) estimating a load on said net,

Claim 2

A method for reducing clock skew in a digital system having at least one integrated-circuit chip containing functional logic circuits and receiving at least one clock signal, comprising the steps of: a) defining a clock tree having a plurality of levels, including one or more upper levels, an initial one of said upper levels receiving said clock signal, and including one or more deep levels, a final one of said deep levels being coupled directly to said functional logic for distributing said clock signal thereto, and defining separate fixed level delays for each level of said tree; b) creating clock logic for said tree and nets for interconnecting said logic, such that said upper levels contain driver circuits having the same, fixed performance for each of said upper levels and also contain terminator circuits having multiple capacitances, and such that said deep levels contain driver circuits having multiple performances, potentially different for every net in said deeplevels; c) for each net in each of said deep levels -- 1) estimating a load on said net, 2) comparing said load to a minimum load necessary to achieve the appropriate one of said level delays, 3) if said load is less than said minimum, connecting a conditional capacitive terminator into said net; d) placing and wiring said functional logic and said clock logic together on said chip; e) for each net in each of said upper levels 1) adjusting the capacitance of the terminator in said net so as to achieve the appropriate one of said level delays; f) for each net in each of said deep levels, 1) if said net has a conditional terminator, adjusting the capacitance of said conditional terminator so as to achieve at least said minimum load, 2) adjusting the performance of the multiple-performance drivers in said net so as to achieve the appropriate one of said level delays.