Integrated circuit device comprising interconnection wiring

Claim 2

An integrated circuit device comprising: a primary power supply wiring (9) connected to a power supply; a primary ground wiring (13) connected to a ground terminal, for holding a reference potential; primary clock driver means (23) for receiving a clock signal from a clock signal input terminal; a first clock signal input wiring (24) for con­necting said clock signal input terminal to said primary clock driver means; a first row including a first secondary clock driver (27a) having a clock signal input terminal con­nected to said primary clock driver means through a second clock signal input wiring (25), a power supply terminal connected to a primary power supply wiring, and a ground terminal connected to a primary ground wiring, and a first group of a plurality of logic ele­ments (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring; a first secondary power supply wiring (15a) for connecting said primary power supply wiring to said power supply terminal of said first secondary clock driver in said first row and to said power supply ter­minals of said first group of logic elements; a first secondary ground wiring (17a) for con­necting said primary ground wiring to said ground terminal of said first secondary clock driver in said first row and to said ground terminals of said logic elements; a second row arranged parallel to a longitudinal direction of said first row, said second row including a second secondary clock driver (27b) having a clock signal input terminal connected to said primary clock driver means through said second clock signal input wiring (25), a power supply terminal connected to said primary power supply wiring, and a ground terminal con­nected to said primary ground wiring, and a second group of a plurality of logic elements (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring; a second secondary power supply wiring (15b) for connecting said primary power supply wiring to said power supply terminal of said second secondary clock driver in said second row and to said power supply ter­minals of said second group of logic elements; a second secondary ground wiring (17b) for connecting said primary ground wiring to said ground terminal of said second secondary clock driver in said second row and to said ground terminals of said logic elements; a second clock signal input wiring (25) for con­necting the input terminals of said first and second secondary clock drivers (27a and 27b) to an output ter­minal of said primary clock driver means; and a clock signal output short-circuiting wiring (35) connected to the clock signal output terminals of said first and second secondary clock drivers (27a and 27b).

Claim 3

A device according to claim 1, characterized in that said first secondary clock driver (27a) included in said first row, and said second secondary clock driver (27b) included in said second row are respectively arranged at one end of said first row and one end of said second row to be adjacent to said primary power supply wiring and said primary ground wiring.

Claim 4

A device according to claim 1, characterized in that said second clock signal input wiring (25) and said clock signal output short-circuiting wiring (35) are arranged on said first secondary clock driver (27a) included in said first row, and said second secondary clock driver (27b) included in said second row along a direction perpendicular to the longitudinal direction of said drivers.

Claim 5

An integrated circuit device comprising: first and second primary power supply wirings (9X and 9Y) commonly connected to a power supply, and divided to be arranged as two lines; first and second primary ground wirings (13X and 13Y) commonly connected to a ground terminal, and divided to be arranged as two lines, for holding a reference potential; primary clock driver means (23) for receiving a clock signal from a clock signal input terminal; a first clock signal input wiring (24) for con­necting said clock signal input terminal to said primary clock driver means; a first row including first and second secondary clock drivers (27a1 and 27a2), said drivers (27a1 and 27a2) respectively having clock signal input terminals connected to said primary clock driver means through second clock signal input wirings, power supply ter­minals respectively connected to said first and second primary power supply wirings (9X and 9Y), and ground terminals respectively connected to said first and second primary ground wirings (13X and 13Y), and a first group of a plurality of logic elements (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings; a first secondary power supply wiring (15a) for respectively connecting said first and second primary power supply wirings (9X and 9Y) to said power supply terminals of said first and second secondary clock drivers (27a1 and 27a2) in said first row and to said power supply terminals of said first group of logic elements; a first secondary ground wiring (17a) for respec­tively connecting said first and second primary ground wirings (13X and 13Y) to said ground terminals of said first and second secondary clock drivers (27a1 and 27a2) in said first row and to said ground terminals of said first group of logic elements; a second row arranged parallel in the longitudinal direction of said first row, said second row including first and second secondary clock drivers (27b1 and 27b2), said drivers (27b1 and 27b2) respectively having clock signal input terminals connected to said primary clock driver means through said second clock signal input wirings (25X and 25Y), power supply terminals con­nected to said first and second primary power supply wirings (9X and 9Y), and ground terminals connected to said first and second primary ground wirings (13X and 13Y), and a second group of a plurality of logic ele­ments (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings; a second secondary power supply wiring (15b) for connecting said first and second primary power supply wirings (9X and 9Y) to said power supply terminals of said first and second secondary clock drivers (27b1 and 27b2) in said second row and to said power supply ter­minals of said second group of logic elements; a second secondary ground wiring (17b) for con­necting said first and second primary ground wirings (13X and 13Y) to said ground terminals of said first and second secondary clock drivers (27b1 and 27b2) in said second row and to said ground terminals of said second group of logic elements; a second clock signal input wirings (25X and 25Y) divided from an output terminal of said primary clock driver means (23), and respectively connected to said first secondary clock drivers (27a1 and 27b1) and second secondary clock drivers (27a2 and 27b2), respectively, included in said first and second rows; a first output short-circuiting wiring (35X) for connecting said first secondary clock drivers (27a1 and 27b1) in said first row and said second row and a second output short-circuiting wiring (35Y) for connecting said second secondary clock drivers (27a2 and 27b2) to each other; and a clock signal wiring (29a1) for commonly con­necting said first clock signal output short-circuiting wiring (35X) to said first and second groups of logic elements corresponding to said first and second rows and included therein, and a second clock signal wiring (29a2) for commonly connecting said second clock signal output short-circuiting wiring (35Y) to said first and second groups of logic elements corresponding to said first and second rows and included therein; a first clock signal wiring for connecting said clock signal output short-circuiting wiring to said first group of logic elements; and a second clock signal wiring for connecting said clock signal output short-circuiting wiring to said second group of logic elements.

Claim 6

An integrated circuit device comprising: first and second primary power supply wirings (9X and 9Y) commonly connected to a power supply, and divided to be arranged as two lines; first and second primary ground wirings (13X and 13Y) commonly connected to a ground terminal, and divided to be arranged as two lines, for holding a reference potential; primary clock driver means (23) for receiving a clock signal from a clock signal input terminal; a first clock signal input wiring (24) for con­necting said clock signal input terminal to said primary clock driver means; a first row including first and second secondary clock drivers (27a1 and 27a2), said drivers (27a1 and 27a2) respectively having clock signal input terminals connected to said primary clock driver means through second clock signal input wirings, power supply ter­minals respectively connected to said first and second primary power supply wirings (9X and 9Y), and ground terminals respectively connected to said first and second primary ground wirings (13X and 13Y), and a first group of a plurality of logic elements (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings; a first secondary power supply wiring (15a) for respectively connecting said first and second primary power supply wirings (9X and 9Y) to said power supply terminals of said first and second secondary clock drivers (27a1 and 27a2) in said first row and to said power supply terminals of said first group of logic elements; a first secondary ground wiring (17a) for respec­tively connecting said first and second primary ground wirings (13X and 13Y) to said ground terminals of said first and second secondary clock drivers (27a1 and 27a2) in said first row and to said ground terminals of said first group of logic elements; a second row arranged parallel in the longitudinal direction of said first row, said second row including first and second secondary clock drivers (27b1 and 27b2), said drivers (27b1 and 27b2) respectively having clock signal input terminals connected to said primary clock driver means through said second clock signal input wirings (25X and 25Y), power supply terminals con­nected to said first and second primary power supply wirings (9X and 9Y), and ground terminals connected to said first and second primary ground wirings (13X and 13Y), and a second group of a plurality of logic ele­ments (19), which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings; a second secondary power supply wiring (15b) for connecting said first and second primary power supply wirings (9X and 9Y) to said power supply terminals of said first and second secondary clock drivers (27b1 and 27b2) in said second row and to said power supply ter­minals of said second group of logic elements; a second secondary ground wiring (17b) for con­necting said first and second primary ground wirings (13X and 13Y) to said ground terminals of said first and second secondary clock drivers (27b1 and 27b2) in said second row and to said ground terminals of said second group of logic elements; a second clock signal input wirings (25X and 25Y) divided from an output terminal of said primary clock driver means (23), and respectively connected to said first secondary clock drivers (27a1 and 27b1) and second secondary clock drivers (27a2 and 27b2), respectively, included in said first and second rows; a first output short-circuiting wiring (35X) for connecting said first secondary clock drivers (27a1 and 27b1) in said first row and said second row and a second output short-circuiting wiring (35Y) for connecting said second secondary clock drivers (27a2 and 27b2) to each other; and a clock signal wiring (29a1) for commonly con­necting said first clock signal output short-circuiting wiring (35X) to said first and second groups of logic elements corresponding to said first and second rows and included therein, and a second clock signal wiring (29a2) for commonly connecting said second clock signal output short-circuiting wiring (35Y) to said first and second groups of logic elements corresponding to said first and second rows and included therein; a first clock signal wiring for connecting said clock signal output short-circuiting wiring to said first group of logic elements; and a second clock signal wiring for connecting said clock signal output short-circuiting wiring to said second group of logic elements.

Claim 7

A device according to claim 4, characterized in that said first and second secondary clock drivers (27a1 and 27a2) included in said first row, and said first and second secondary clock drivers (27b1 and 27b2) included in said second row are respectively arranged at ends of said first and second rows to be adjacent to said first and second primary power supply wirings (9X and 9Y) and said first and second primary ground wirings (13X and 13Y).

Claim 8

A device according to claim 4, characterized in that said clock signal input wirings (25X and 25Y) and said clock signal output short-circuiting wirings (35X and 35Y) are respectively arranged on said first and second secondary clock drivers (27a1 and 27b1, and 27a2 and 27b2) respectively included in said first and second rows along a direction perpendicular to the longitudinal direction of said rows.