US5668041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device having a capacitor
Assignee: Renesas Electronics Corp
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Filing: 1996-04-15
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Granted: 1997-09-16
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Expires: 2016-04-15
Abstract
Abstract According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
Inventors
- 👤 Tomonori Okudaira
- 👤 Takeharu Kuroiwa
- 👤 Nobuo Fujiwara
- 👤 Keiichiro Kashihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10P; H10P14/00; H10P14/40; Y; Y10; Y10S; Y10S257/00; Y10S257/915; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
172 words
A method of manufacturing a semiconductor device comprising the steps of: forming an impurity region on a main surface of semiconductor substrate, forming an interlayer insulation film on the main surface of said semiconductor substrate to cover said impurity region, including a first contact hole of a first diameter and reaching said impurity region, and a second contact hole of a second diameter greater than said first diameter and provided above said first contact hole in communication therewith, forming a buried conductive layer filling said first contact hole, and in contact with a part of the top face of said impurity region, forming a lower electrode layer, filling said second contact hole, in contact with the surface of said buried conductive layer, and having a top face substantially flush with a top face of said interlayer insulation film, forming a high dielectric film of a high dielectric constant material on said interlayer insulation film to come into contact with said lower electrode, and forming an upper electrode on said high dielectric film.
Claim 2
Independent Claim
172 words
A method of manufacturing a semiconductor device comprising the steps of: forming an impurity region on a main surface of semiconductor substrate, forming an interlayer insulation film on the main surface of said semiconductor substrate to cover said impurity region, including a first contact hole of a first diameter and reaching said impurity region, and a second contact hole of a second diameter greater than said first diameter and provided above said first contact hole in communication therewith, forming a buried conductive layer filling said first contact hole, and in contact with a part of the top face of said impurity region, forming a lower electrode layer, filling said second contact hole, in contact with the surface of said buried conductive layer, and having a top face substantially flush with a top face of said interlayer insulation film, forming a high dielectric film of a high dielectric constant material on said interlayer insulation film to come into contact with said lower electrode, and forming an upper electrode on said high dielectric film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |